CS8420-DSZR Cirrus Logic Inc, CS8420-DSZR Datasheet - Page 86

• Manufacturer Part Number: CS8420-DSZR
• Description: IC,Digital Audio Sample Rate Converter,SOP,28PIN
• Manufacturer: Cirrus Logic Inc

CS8420
transmitter can read out data that had previously accumulated, allowing the FIFO to empty out. If the FIFO
becomes completely empty, zeros are transmitted until a complete message is written into the FIFO.
Mode 4 is not fail-safe; the FIFO can still get completely full if there isn't enough “zero-padding” between
incoming messages. It is up to the user to provide proper padding, as defined below:
Minimum padding
= (Fsi/Fso - 1)*[8N + (N-1)*IF +9] + 9
where N is the number of IUs in the message, IF is the number of filler bits between each IU, and Fso ≤ Fsi.
Example 1: Fsi/Fso = 2, N=4, IF=1: minimum proper padding is 53 bits.
Example 2: Fsi/Fso = 1, N=4, IF=7: min proper padding is 9 bits.
The CS8420 detects when an overwrite has occurred in the FIFO, and synchronously resets the entire
FIFO structure to prevent corrupted U data from being merged into the transmitted AES3 data stream.
The CS8420 can be configured to generate an interrupt when this occurs.
Mode 4 is recommended for properly formatted U data where mode 3 cannot provide acceptable perfor-
mance, either because of a too-extreme Fsi/Fso ratio, or because it's unacceptable to change the lengths
of filler segments. Mode 4 provides error-free performance over the complete range of Fsi/Fso ratios (pro-
vided that the input messages are properly zero-padded for Fsi > Fso).
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