CS8420-DSZR Cirrus Logic Inc, CS8420-DSZR Datasheet - Page 44

• Manufacturer Part Number: CS8420-DSZR
• Description: IC,Digital Audio Sample Rate Converter,SOP,28PIN
• Manufacturer: Cirrus Logic Inc

44
10.15 Receiver Error (10h) (Read Only)
QCRC
CCRC
UNLOCK
V
CONF
BIP
PAR
7
0
QCRC
This register contains the AES3 receiver and PLL status bits. Unmasked bits will go high on
occurrence of the error, and will stay high until the register is read. Reading the register resets
all bits to 0, unless the error source is still true. Bits that are masked off in the receiver error
mask register will always be 0 in this register. This register defaults to 00.
0 - No error
1 - Error
Channel Status Block Cyclic Redundancy Check bit. Updated on CS block boundaries.
This bit is valid in Professional mode only.
0 - No error
1 - Error
PLL lock status bit. Updated on CS block boundaries.
0 - PLL locked
1 - PLL out of lock
Received AES3 Validity bit status. Updated on sub-frame boundaries.
0 - Data is valid and is normally linear coded PCM audio
1 - Data is invalid, or may be valid compressed audio
0 - No error
1 - Confidence error. This indicates that the received data eye opening is less than
half a bit period, indicating a poor link that is not meeting specifications.
Bi-phase error bit. Updated on sub-frame boundaries.
0 - No error
1 - Bi-phase error. This indicates an error in the received bi-phase coding.
0 - No error
1 - Parity error
Q-subcode data CRC error has occurred. Updated on Q-subcode block boundaries.
Confidence bit. Updated on sub-frame boundaries.
Parity bit. Updated on sub-frame boundaries.
6
CCRC
5
UNLOCK
4
3
V
CONF
2
BIP
1
CS8420
DS245F4
PAR
0