DSPIC30F5011-20I/PTG Microchip Technology, DSPIC30F5011-20I/PTG Datasheet - Page 62

• Manufacturer Part Number: DSPIC30F5011-20I/PTG
• Description: IC, DSC, 16BIT, 66KB, 40MHZ 5.5V TQFP-64
• Manufacturer: Microchip Technology
• Series: DsPIC30Fr

Specifications of DSPIC30F5011-20I/PTG

• Core Frequency: 40MHz
• Core Supply Voltage: 5.5V
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of I/o's: 52
• Flash Memory Size: 66KB
• Supply Voltage Range: 2.5V To 5.5V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

dsPIC30F5011/5013
FIGURE 8-2:
8.2
The use of the ADPCFG and TRIS registers control the
operation of the A/D port pins. The port pins that are
desired
corresponding TRIS bit set (input). If the TRIS bit is
cleared (output), the digital output level (V
will be converted.
When reading the Port register, all pins configured as
analog input channels will read as cleared (a low level).
Pins configured as digital inputs will not convert an
analog input. Analog levels on any pin that is defined as
a digital input (including the ANx pins) may cause the
input buffer to consume current that exceeds the
device specifications.
DS70116H-page 62
Configuring Analog Port Pins
as
analog
Data Bus
WR TRIS
WR LAT +
WR Port
BLOCK DIAGRAM OF A SHARED PORT STRUCTURE
inputs
Read Port
Peripheral Input Data
Peripheral Module Enable
Peripheral Output Enable
Peripheral Output Data
Read TRIS
Peripheral Module
PIO Module
must
Read LAT
TRIS Latch
Data Latch
D
D
CK
CK
have
OH
Q
Q
or V
their
OL
)
8.2.1
One instruction cycle is required between a port
direction change or port write operation and a read
operation of the same port. Typically this instruction
would be a NOP.
EXAMPLE 8-1:
MOV
MOV
NOP
btss
1
0
1
0
0xFF00, W0
W0, TRISB
PORTB, #13
Output Data
Output Enable
I/O PORT WRITE/READ TIMING
Output Multiplexers
Input Data
; additional instruction
; Configure PORTB<15:8>
; as inputs
; and PORTB<7:0> as outputs
; bit test RB13 and skip if
PORT WRITE/READ
EXAMPLE
I/O Cell
© 2008 Microchip Technology Inc.
cycle
set
I/O Pad