DSPIC30F5011-20I/PTG Microchip Technology, DSPIC30F5011-20I/PTG Datasheet - Page 121

• Manufacturer Part Number: DSPIC30F5011-20I/PTG
• Description: IC, DSC, 16BIT, 66KB, 40MHZ 5.5V TQFP-64
• Manufacturer: Microchip Technology
• Series: DsPIC30Fr

Specifications of DSPIC30F5011-20I/PTG

• Core Frequency: 40MHz
• Core Supply Voltage: 5.5V
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of I/o's: 52
• Flash Memory Size: 66KB
• Supply Voltage Range: 2.5V To 5.5V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

18.3
18.3.1
The DCI
setting/clearing the DCIEN control bit in the DCICON1
SFR. Clearing the DCIEN control bit has the effect of
resetting the module. In particular, all counters
associated with CSCK generation, frame sync and the
DCI buffer control unit are Reset.
The DCI clocks are shutdown when the DCIEN bit is
cleared.
When enabled, the DCI controls the data direction for
the four I/O pins associated with the module. The Port,
LAT and TRIS register values for these I/O pins are
overridden by the DCI module when the DCIEN bit is set.
It is also possible to override the CSCK pin separately
when the bit clock generator is enabled. This permits
the bit clock generator to operate without enabling the
rest of the DCI module.
18.3.2
The WS<3:0> word size selection bits in the DCICON2
SFR determine the number of bits in each DCI data
word. Essentially, the WS<3:0> bits determine the
counting period for a 4-bit counter clocked from the
CSCK signal.
Any data length, up to 16-bits, may be selected. The
value loaded into the WS<3:0> bits is one less the
desired word length. For example, a 16-bit data word
size is selected when WS<3:0> = 1111.
18.3.3
The frame sync generator (COFSG) is a 4-bit counter
that sets the frame length in data words. The frame
sync generator is incremented each time the word size
counter is reset (refer to Section 18.3.2 “Word Size
Selection Bits”). The period for the frame synchroni-
zation generator is set by writing the COFSG<3:0>
control bits in the DCICON2 SFR. The COFSG period
in clock cycles is determined by the following formula:
EQUATION 18-1:
Frame lengths, up to 16 data words, may be selected.
The frame length in CSCK periods can vary up to a
maximum of 256 depending on the word size that is
selected.
© 2008 Microchip Technology Inc.
Note:
Note:
Frame Length = Word Length • (FSG Value + 1)
DCI Module Operation
MODULE ENABLE
WORD SIZE SELECTION BITS
These WS<3:0> control bits are used only
in the Multi-Channel and I
bits have no effect in AC-Link mode since
the data slot sizes are fixed by the protocol.
FRAME SYNC GENERATOR
The COFSG control bits will have no effect
in AC-Link mode since the frame length is
set to 256 CSCK periods by the protocol.
module
is enabled
COFSG PERIOD
2
or disabled
S modes. These
by
18.3.4
The type of frame sync signal is selected using the
Frame
(COFSM<1:0>) in the DCICON1 SFR. The following
operating modes can be selected:
• Multi-Channel mode
• I
• AC-Link mode (16-bit)
• AC-Link mode (20-bit)
The operation of the COFSM control bits depends on
whether the DCI module generates the frame sync
signal as a master device, or receives the frame sync
signal as a slave device.
The master device in a DSP/codec pair is the device
that generates the frame sync signal. The frame sync
signal initiates data transfers on the CSDI and CSDO
pins and usually has the same frequency as the data
sample rate (COFS).
The DCI module is a frame sync master if the COFSD
control bit is cleared and is a frame sync slave if the
COFSD control bit is set.
18.3.5
When the DCI module is operating as a frame sync
master device (COFSD = 0), the COFSM mode bits
determine the type of frame sync pulse that is
generated by the frame sync generator logic.
A new COFS signal is generated when the frame sync
generator resets to ‘0’.
In the Multi-Channel mode, the frame sync pulse is
driven high for the CSCK period to initiate a data
transfer. The number of CSCK cycles between
successive frame sync pulses will depend on the word
size and frame sync generator control bits. A timing
diagram for the frame sync signal in Multi-Channel
mode is shown in Figure 18-2.
In the AC-Link mode of operation, the frame sync
signal has a fixed period and duty cycle. The AC-Link
frame sync signal is high for 16 CSCK cycles and is low
for 240 CSCK cycles. A timing diagram with the timing
details at the start of an AC-Link frame is shown in
Figure 18-3.
In the I
cycle is generated. The period of the I
signal in CSCK cycles is determined by the word size
and frame sync generator control bits. A new I
transfer boundary is marked by a high-to-low or a
low-to-high transition edge on the COFS pin.
2
dsPIC30F5011/5013
S mode
2
S mode, a frame sync signal having a 50% duty
Synchronization
FRAME SYNC MODE
CONTROL BITS
MASTER FRAME SYNC
OPERATION
mode
DS70116H-page 121
2
control
S frame sync
2
S data
bits