DSPIC30F5011-20I/PTG Microchip Technology, DSPIC30F5011-20I/PTG Datasheet - Page 15

• Manufacturer Part Number: DSPIC30F5011-20I/PTG
• Description: IC, DSC, 16BIT, 66KB, 40MHZ 5.5V TQFP-64
• Manufacturer: Microchip Technology
• Series: DsPIC30Fr

Specifications of DSPIC30F5011-20I/PTG

• Core Frequency: 40MHz
• Core Supply Voltage: 5.5V
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of I/o's: 52
• Flash Memory Size: 66KB
• Supply Voltage Range: 2.5V To 5.5V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2.0
2.1
This section contains a brief overview of the CPU
architecture
hard-ware and programming information, please refer
to
(DS70046) and the “dsPIC30F/33F Programmer’s
Reference Manual” (DS70157), respectively.
The core has a 24-bit instruction word. The Program
Counter (PC) is 23 bits wide with the Least Significant
bit (LSb) always clear (refer to Section 3.1 “Program
Address Space”), and the Most Significant bit (MSb)
is ignored during normal program execution, except for
certain specialized instructions. Thus, the PC can
address up to 4M instruction words of user program
space. An instruction prefetch mechanism is used to
help maintain throughput. Program loop constructs,
free from loop count management overhead, are
supported using the DO and REPEAT instructions, both
of which are interruptible at any point.
The working register array consists of 16 x 16-bit
registers, each of which can act as data, address or
offset registers. One working register (W15) operates
as a software Stack Pointer for interrupts and calls.
The data space is 64 Kbytes (32K words) and is split
into two blocks, referred to as X and Y data memory.
Each block has its own independent Address
Generation Unit (AGU). Most instructions operate
solely through the X memory, AGU, which provides the
appearance of a single unified data space. The
Multiply-Accumulate (MAC) class of dual source DSP
instructions operate through both the X and Y AGUs,
splitting the data address space into two parts (see
Section 3.2 “Data Address Space”). The X and Y
data space boundary is device specific and cannot be
altered by the user. Each data word consists of 2 bytes,
and most instructions can address data either as words
or bytes.
© 2008 Microchip Technology Inc.
Note:
the “dsPIC30F
CPU ARCHITECTURE
OVERVIEW
Core Overview
This data sheet summarizes features of
this group of dsPIC30F devices and is not
intended to be a complete reference
source. For more information on the CPU,
peripherals, register descriptions and
general device functionality, refer to the
“dsPIC30F Family Reference Manual”
(DS70046). For more information on the
device instruction set and programming,
refer to the “dsPIC30F/33F Programmer’s
Reference Manual” (DS70157).
of
the
Family
dsPIC30F.
Reference
For
additional
Manual”
There are two methods of accessing data stored in
program memory:
• The upper 32 Kbytes of data space memory can
• Linear indirect access of 32K word pages within
Overhead-free circular buffers (modulo addressing) are
supported in both X and Y address spaces. This is
primarily intended to remove the loop overhead for
DSP algorithms.
The X AGU also supports bit-reversed addressing on
destination effective addresses to greatly simplify input
or output data reordering for radix-2 FFT algorithms.
Refer to Section 5.0 “Address Generator Units” for
details on modulo and bit-reversed addressing.
The core supports Inherent (no operand), Relative,
Literal, Memory Direct, Register Direct, Register
Indirect, Register Offset and Literal Offset Addressing
modes. Instructions are associated with predefined
Addressing modes, depending upon their functional
requirements.
For most instructions, the core is capable of executing
a data (or program data) memory read, a working
register (data) read, a data memory write and a
program (instruction) memory read per instruction
cycle. As a result, 3-operand instructions are
supported, allowing C = A + B operations to be
executed in a single cycle.
A DSP engine has been included to significantly
enhance the core arithmetic capability and throughput.
It features a high-speed 17-bit by 17-bit multiplier, a
40-bit ALU, two 40-bit saturating accumulators and a
40-bit
accumulator or any working register can be shifted up
to 15 bits right, or 16 bits left in a single cycle. The DSP
instructions
instructions and have been designed for optimal
real-time performance. The MAC class of instructions
can concurrently fetch two data operands from memory
while multiplying two W registers. To enable this
concurrent fetching of data operands, the data space
has been split for these instructions and linear for all
others. This has been achieved in a transparent and
flexible manner, by dedicating certain working registers
to each address space for the MAC
instructions.
be mapped into the lower half (user space) of
program space at any 16K program word
boundary, defined by the 8-bit Program Space
Visibility Page (PSVPAG) register. This lets any
instruction access program space as if it were
data space, with a limitation that the access
requires an additional cycle. Moreover, only the
lower 16 bits of each instruction word can be
accessed using this method.
program space is also possible using any working
register, via table read and write instructions.
Table read and write instructions can be used to
access all 24 bits of an instruction word.
dsPIC30F5011/5013
bidirectional
operate
barrel
seamlessly
shifter.
DS70116H-page 15
with
Data
all
class of
in
other
the