DSPIC30F5011-20I/PTG Microchip Technology, DSPIC30F5011-20I/PTG Datasheet - Page 37

• Manufacturer Part Number: DSPIC30F5011-20I/PTG
• Description: IC, DSC, 16BIT, 66KB, 40MHZ 5.5V TQFP-64
• Manufacturer: Microchip Technology
• Series: DsPIC30Fr

Specifications of DSPIC30F5011-20I/PTG

• Core Frequency: 40MHz
• Core Supply Voltage: 5.5V
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of I/o's: 52
• Flash Memory Size: 66KB
• Supply Voltage Range: 2.5V To 5.5V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.0
The dsPIC30F Sensor and General Purpose Family
has up to 41 interrupt sources and 4 processor
exceptions (traps) which must be arbitrated based on a
priority scheme.
The CPU is responsible for reading the Interrupt Vector
Table (IVT) and transferring the address contained in
the interrupt vector to the program counter. The
interrupt vector is transferred from the program data
bus into the program counter via a 24-bit wide
multiplexer on the input of the program counter.
The Interrupt Vector Table (IVT) and Alternate Interrupt
Vector Table (AIVT) are placed near the beginning of
program memory (0x000004). The IVT and AIVT are
shown in Figure 4-1.
The
pre-processing
exceptions prior to them being presented to the
processor core. The peripheral interrupts and traps are
enabled, prioritized and controlled using centralized
Special Function Registers:
• IFS0<15:0>, IFS1<15:0>, IFS2<15:0>
• IEC0<15:0>, IEC1<15:0>, IEC2<15:0>
• IPC0<15:0>... IPC10<7:0>
• IPL<3:0>
• INTCON1<15:0>, INTCON2<15:0>
© 2008 Microchip Technology Inc.
Note:
All interrupt request flags are maintained in these
three registers. The flags are set by their
respective peripherals or external signals, and
they are cleared via software.
All interrupt enable control bits are maintained in
these three registers. These control bits are used
to individually enable interrupts from the
peripherals or external signals.
The user assignable priority level associated with
each of these 41 interrupts is held centrally in
these twelve registers.
The current CPU priority level is explicitly stored
in the IPL bits. IPL<3> is present in the CORCON
register, whereas IPL<2:0> are present in the
STATUS register (SR) in the processor core.
Global interrupt control functions are derived from
these two registers. INTCON1 contains the con-
trol and status flags for the processor exceptions.
The INTCON2 register controls the external
interrupt request signal behavior and the use of
the alternate vector table.
interrupt
INTERRUPTS
This data sheet summarizes features of
this group of dsPIC30F devices and is not
intended to be a complete reference
source. For more information on the CPU,
peripherals, register descriptions and
general device functionality, refer to the
“dsPIC30F Family Reference Manual”
(DS70046).
the
controller
interrupts
is
responsible
and
processor
for
• INTTREG<15:0>
All interrupt sources can be user assigned to one of 7
priority levels, 1 through 7, via the IPCx registers. Each
interrupt source is associated with an interrupt vector,
as shown in Table 4-1. Levels 7 and 1 represent the
highest and lowest maskable priorities, respectively.
If the NSTDIS bit (INTCON1<15>) is set, nesting of
interrupts is prevented. Thus, if an interrupt is currently
being serviced, processing of a new interrupt is
prevented even if the new interrupt is of higher priority
than the one currently being serviced.
Certain interrupts have specialized control bits for
features like edge or level triggered interrupts,
interrupt-on-change, etc. Control of these features
remains within the peripheral module which generates
the interrupt.
The DISI instruction can be used to disable the
processing of interrupts of priorities 6 and lower for a
certain number of instructions, during which the DISI bit
(INTCON2<14>) remains set.
When an interrupt is serviced, the PC is loaded with the
address stored in the vector location in program
memory that corresponds to the interrupt. There are 63
different vectors within the IVT (refer to Table 4-1).
These vectors are contained in locations 0x000004
through 0x0000FE of program memory (refer to
Table 4-1). These locations contain 24-bit addresses
and in order to preserve robustness, an address error
trap will take place should the PC attempt to fetch any
of these words during normal execution. This prevents
execution of random data as a result of accidentally
decrementing a PC into vector space, accidentally
mapping a data space address into vector space or the
PC rolling over to 0x000000 after reaching the end of
implemented program memory space. Execution of a
GOTO instruction to this vector space will also generate
an address error trap.
The associated interrupt vector number and the
new CPU interrupt priority level are latched into
vector number (VECNUM<5:0>) and interrupt
level (ILR<3:0>) bit fields in the INTTREG
register. The new interrupt priority level is the
priority of the pending interrupt.
Note:
Note:
Note:
dsPIC30F5011/5013
Interrupt flag bits get set when an interrupt
condition occurs, regardless of the state of
its
software should ensure the appropriate
interrupt flag bits are clear prior to
enabling an interrupt.
Assigning a priority level of ‘0’ to an
interrupt source is equivalent to disabling
that interrupt.
The IPL bits become read-only whenever
the NSTDIS bit has been set to ‘1’.
corresponding
enable
DS70116H-page 37
bit.
User