MC56F8255VLD Freescale Semiconductor, MC56F8255VLD Datasheet - Page 19

• Manufacturer Part Number: MC56F8255VLD
• Description: DSC 64K FLASH 60MHZ 44-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8255VLD

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 44-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 35
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 4 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Freescale Semiconductor
CMPA_M0)
CMPA_P2)
(CMPC_O)
(GPIOD3)
(GPIOD4)
GPIOA0
GPIOA1
(ANA0&
(ANA1&
RESET
Signal
Name
TMS
LQFP
44
43
2
8
9
Table 5. MC56F825x/MC56F824x Signal and Package Information (continued)
LQFP
48
47
10
2
9
LQFP
64
63
13
14
2
MC56F825x/MC56F824x Digital Signal Controller, Rev. 3
Open-drain
Output
Output
Output
Output
Output
Input/
Input/
Input/
Input/
Type
Input
Input
Input
input
enabled
enabled
enabled
enabled
internal
internal
internal
internal
During
Reset
pullup
pullup
pullup
pullup
Input,
Input,
Input,
Input,
State
Test Mode Select Input — This input pin is used to sequence the
JTAG TAP controller’s state machine. It is sampled on the rising
edge of TCK and has an on-chip pullup resistor.
Port D GPIO — This GPIO pin can be individually programmed as
an input or output pin.
After reset, the default state is TMS
Note: Always tie the TMS pin to VDD through a 2.2K resistor if need
to keep on-board debug capability. Otherwise directly tie to VDD
Reset — This input is a direct hardware reset on the processor.
When RESET is asserted low, the device is initialized and placed in
the reset state. A Schmitt-trigger input is used for noise immunity.
The internal reset signal is deasserted synchronous with the
internal clocks after a fixed number of internal clocks.
Port D GPIO — This GPIO pin can be individually programmed as
an input or open-drain output pin.If RESET functionality is disabled
in this mode and the chip can be reset only via POR, COP reset, or
software reset.
After reset, the default state is RESET.
Port A GPIO — This GPIO pin can be individually programmed as
an input or output pin.
ANA0 and CMPA_P2 — Analog input to channel 0 of ADCA and
positive input 2 of analog comparator A.
CMPC_O— Analog comparator C output
When used as an analog input, the signal goes to the ANA0 and
CMPA_P2.
After reset, the default state is GPIOA0.
Port A GPIO — This GPIO pin can be individually programmed as
an input or output pin.
ANA1 and CMPA_M0 — Analog input to channel 1of ADCA and
negative input 0 of analog comparator A.
When used as an analog input, the signal goes to the ANA1 and
CMPA_M0.
After reset, the default state is GPIOA1.
Signal Description
Signal/Connection Descriptions
19