AD9553BCPZ Analog Devices Inc, AD9553BCPZ Datasheet - Page 35

• Manufacturer Part Number: AD9553BCPZ
• Description: IC INTEGER-N CLCK GEN 32LFCSP
• Manufacturer: Analog Devices Inc

Specifications of AD9553BCPZ

• Clock Ic Type: PLL Clock Driver
• Ic Interface Type: 3 Wire, Serial
• Frequency: 710MHz
• No. Of Outputs: 2
• Supply Current: 162mA
• Supply Voltage Range: 0V To 3.3V
• Digital Ic Case Style: LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

REGISTER MAP DESCRIPTIONS
Control bit functions are active high unless stated otherwise. Register address values are always hexadecimal unless otherwise indicated.
Serial Port Control (Register 0x00 to Register 0x05)
Table 28.
Address
0x00
0x04
0x05
PLL Charge Pump and PFD Control (Register 0x0A to Register 0x0D)
Table 29.
Address
0x0A
0x0B
Bit
7
6
5
4
[3:0]
[7:1]
0
[7:1]
0
Bit
[7:0]
7
6
[5:4]
3
2
1
0
Bit Name
Unused
LSB first
Soft reset
Unused
Unused
Unused
Readback control
Unused
I/O update
Bit Name
Charge pump current control
Enable SPI control of charge
pump current
Enable SPI control of
antibacklash period
Charge pump mode
Disable charge pump
PFD feedback input edge control
PFD reference input edge control
Force VCO to midpoint frequency
Description
Forced to Logic 0 internally, which enables 3-wire mode only.
Bit order for SPI port.
0 = most significant bit and byte first (default).
1 = least significant bit and byte first.
Software initiated reset (register values set to default). This is an autoclearing bit.
Forced to Logic 1 internally, which enables 16-bit mode (the only mode supported
by the device).
Mirrored version of the contents of Register 0x00[7:4] (that is, Bits[3:0] = Bits[7:4]).
Unused.
For buffered registers, serial port readback reads from actual (active) registers instead
of from the buffer.
0 = reads values currently applied to the internal logic of the device (default).
1 = reads buffered values that take effect on next assertion of I/O update.
Unused.
Writing a 1 to this bit transfers the data in the serial I/O buffer registers to the
internal control registers of the device. This is an autoclearing bit.
Description
These bits set the magnitude of the PLL charge pump current. The granularity is
~3.5 μA with a full-scale magnitude of ~900 μA. Default is 0x80, or ~448 μA.
Register 0x0A is ineffective unless Register 0x0B[7] = 1.
Controls the functionality of Register 0x0A.
0 = charge pump current based on A3 to A0 pins and Y5 to Y0 pins per Table 16 (default).
1 = charge pump current defined by Register 0x0A.
Controls the functionality of Register 0x0D[7:6].
0 = the device automatically controls the antibacklash period (default).
1 = antibacklash period defined by Register 0x0D[7:6].
Controls the mode of the PLL charge pump.
00 = tristate.
01 = pump up.
10 = pump down.
11 = normal (default).
Disables the charge pump (functionally equivalent to Register 0x0B[5:4] = 00).
0 = normal operation (default).
1 = disable charge pump.
Selects the polarity of the active edge of the PLL’s feedback input.
0 = positive edge (default).
1 = negative edge.
Selects the polarity of the active edge of the PLL’s reference input.
0 = positive edge (default).
1 = negative edge.
Selects VCO control voltage functionality.
0 = normal VCO operation (default).
1 = force VCO control voltage to midscale.
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AD9553