AD9553BCPZ Analog Devices Inc, AD9553BCPZ Datasheet - Page 20

• Manufacturer Part Number: AD9553BCPZ
• Description: IC INTEGER-N CLCK GEN 32LFCSP
• Manufacturer: Analog Devices Inc

Specifications of AD9553BCPZ

• Clock Ic Type: PLL Clock Driver
• Ic Interface Type: 3 Wire, Serial
• Frequency: 710MHz
• No. Of Outputs: 2
• Supply Current: 162mA
• Supply Voltage Range: 0V To 3.3V
• Digital Ic Case Style: LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9553
Although the SPI and pin control modes are functionally
independent, it is possible to mix the control modes. For
example, suppose that pin control satisfies all of the require-
ments for an application except for the value of the P
(which is associated with OUT2). The user could do the
following:
•
•
•
•
•
In this way, the function muxes that control P
the appropriate register bits as the source for controlling the
dividers, while all the other function muxes select the pin decoders
as the source for controlling the other functions. Note that the
dividers remain under register control until the user activates
Activate SPI mode via the frequency selection pins.
Program the desired P
map (Register 0x15 to Register 0x18).
Set the enable SPI control bit for the output dividers
(Register 0x14[2] = 1).
Calibrate the VCO by enabling SPI control of VCO
calibration (Register 0x0E[2] = 1), then issue a calibrate
command (Register 0x0E[7] = 1). Be sure to program the
N divider, R dividers, ÷5 dividers, and ×2 multipliers to the
values defined by the Ax and Yx pin settings prior to cali-
brating the VCO.
Restore the original settings to the frequency selection pins
to invoke the desired frequency selection.
FUNCTION
FUNCTION
FUNCTION
CONTROL
ABC BITS
0
XYZ BITS
OUTPUT
, P
MODE
BITS
1
, and P
SPI CONTROLLER
REGISTER MAP
2
SPI/OM[2:0]
ENABLE SPI CONTROL
ENABLE SPI CONTROL
ENABLE SPI CONTROL
values in the register
OF FUNCTIONING XYZ
OF OUTPUT ABC BITS
3
OF OUTPUT MODE
1
3
0
0
, P
3
3
1
, and P
2
SPI MODE
divider
Figure 28. Control Mode Diagram
2
select
Rev. A | Page 20 of 44
CONTROL
DECODER
OUTPUT
MODE
3
A[3:0]
PINS DECODER
4
FREQUENCY
SELECTION
SPI mode and writes Register 0x14[2] = 0, thereby causing the
function mux to use the frequency selection pins decoder as the
source for controlling the dividers, instead of the register map.
DESCRIPTION OF FUNCTIONAL BLOCKS
Reference Inputs
The default configuration of the AD9553 provides up to two
single-ended input clock receivers, REFA and REFB, which are
high impedance CMOS inputs. In applications that require redun-
dant reference clocks with switchover capability, REFA is the
primary reference and REFB the secondary reference. Alternatively,
the user can configure the input (via the serial I/O port) as a
single differential receiver. In this case, the REFB input func-
tions as REFA (the complementary input of REFA). Note that
in this configuration the device operates with only one reference
input clock, eliminating the need for switchover functionality.
XTAL Input
The AD9553 accepts an optional 25 MHz crystal resonator
connected across the XTAL pins. Alternatively, it accepts a
single-ended clock source (CMOS compatible) connected to
either one of the XTAL input pins (in this case, the unused
input remains floating). Unless otherwise programmed, the
device expects the crystal to have a specified load capacitance
of 10 pF (default). The AD9553 provides the necessary load
capacitance internally. The internal load capacitance consists
Y[5:0]
6
FUNCTION
MUXES
0
1
0
1
0
1
OUTPUT MODE
CONTROL
FUNCTION
FUNCTION
ABC
FUNCTION
XYZ