MAX5978ETJ+ Maxim Integrated Products, MAX5978ETJ+ Datasheet - Page 33

Hot Swap & Power Distribution 0-16V HOTSWAP CONTLR W/10BIT CUR VOLT MON

MAX5978ETJ+

Manufacturer Part Number
MAX5978ETJ+
Description
Hot Swap & Power Distribution 0-16V HOTSWAP CONTLR W/10BIT CUR VOLT MON
Manufacturer
Maxim Integrated Products
Datasheet

Specifications of MAX5978ETJ+

Product
Controllers & Switches
Supply Voltage (max)
16 V
Supply Voltage (min)
0 V
Power Dissipation
2759 mW
Operating Temperature Range
- 40 C to + 85 C
Mounting Style
SMD/SMT
Supply Current
2.5 mA
Package / Case
TQFN-32
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Table 52. LED State Register
Figure 4. Serial-Interface Timing Details
The device features an I
consisting of a serial data line (SDA) and a serial clock
line (SCL). SDA and SCL allow bidirectional communica-
tion between the device and the master device at clock
rates from 100kHz to 400kHz. The I
several devices (e.g., more than one device, or other I
devices in addition to the device) attached simultane-
ously. The A0 and A1 inputs set one of nine possible I
addresses (see Table 53).
The 2-wire communication is fully compatible with exist-
ing 2-wire serial interface systems; Figure 4 shows
the interface timing diagram. The device is a transmit/
receive slave-only device, relying upon a master device
Description:
Register Title:
Register Address:
t
HD:STA
SDA
SCL
Bit 7
R
CONDITION
Current, Voltage Monitor, and 4 LED Drivers
START
t
SU:DAT
0 to 16V, Hot-Swap Controller with 10-Bit
Bit 6
R
t
LOW
t
R
2
LED state register
LED_state
0x45
C-compatible serial interface
t
HIGH
Bit 5
R
I
2
t
F
C Serial Interface
2
C bus can have
t
HD:DAT
Bit 4
R
Voltage
2
2
t
SU:STA
LED4
C
C
Bit 3
R
REPEATED START
CONDITION
to generate a clock signal. The master device (typically
a microcontroller) initiates data transfer on the bus and
generates SCL to permit that transfer.
A master device communicates to the device by trans-
mitting the proper address followed by command and/
or data words. Each transmit sequence is framed by
a START (S) or Repeated START (SR) condition and a
STOP (P) condition. Each word transmitted over the bus
is 8 bits long and is always followed by an acknowledge
pulse.
SCL is a logic input, while SDA is a logic input/open-
drain output. SCL and SDA both require external pullup
resistors to generate the logic-high voltage. Use 4.7kI
for most applications.
Voltage
LED3
Bit 2
R
t
HD:STA
Voltage
LED2
Bit 1
R
t
SU:STO
Voltage
LED1
Bit 0
R
CONDITION
STOP
t
BUF
CONDITION
RESET
VALUE
START
33

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