Si5351A-A-GM Silicon Laboratories Inc, Si5351A-A-GM Datasheet - Page 31

• Manufacturer Part Number: Si5351A-A-GM
• Description: Clock Generators & Support Products AnyRate 2 PLL 125MHz Clk&I2C 8out
• Manufacturer: Silicon Laboratories Inc
• Type: Any Frequency CMOS Clock Generatorr

Specifications of Si5351A-A-GM

• Mounting Style: SMD/SMT
• Max Input Freq: 0.008 MHz
• Max Output Freq: 133 MHz
• Number Of Outputs: 8
• Operating Supply Voltage: 3.3 V
• Operating Temperature Range: - 40 C to + 85 C
• Supply Current: 25 mA
• Package / Case: QFN-20
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Reset value = 0000 0000
Register 17. CLK1 Control
Name
3:2
1:0
Bit
Type
7
6
5
4
Bit
CLK1_IDRV[1:0] CLK1 Output Rise and Fall time / Drive Strength Control.
CLK1_SRC[1:0] Output Clock 1 Input Source.
CLK1_PDN
CLK1_PDN
MS1_SRC
CLK1_INV
MS1_INT
Name
R/W
D7
MS1_INT
Clock 1 Power Down.
This bit allows powering down the CLK1 output driver to conserve power when the out-
put is unused.
0: CLK1 is powered up.
1: CLK1 is powered down.
MultiSynth 1 Integer Mode.
This bit can be used to force MS1 into Integer mode to improve jitter performance. Note
that the fractional mode is necessary when a delay offset is specified for CLK1.
0: MS1 operates in fractional division mode.
1: MS1 operates in integer mode.
MultiSynth Source Select for CLK1.
0: Select PLLA as the source for MultiSynth0.
1: Select PLLB (Si5351A/C only) or VCXO (Si5351B only) MultiSynth0.
Output Clock 1 Invert.
0: Output Clock 1 is not inverted.
1: Output Clock 1 is inverted.
These bits determine the input source for CLK1.
00: Select the XTAL as the clock source for CLK1. This option by-passes both synthesis
stages (PLL/VCXO & MultiSynth) and connects CLK1 directly to the oscillator which
generates an output frequency determined by the XTAL frequency.
01: Select CLKIN as the clock source for CLK1. This by-passes both synthesis stages
(PLL/VCXO & MultiSynth) and connects CLK1 directly to the CLKIN input. This essen-
tially creates a buffered output of the CLKIN input.
10: Reserved. Do not select this option.
11: Select MultiSynth 0 as the source for CLK1. Select this option when using the
Si5351 to generate free-running or synchronous clocks.
00: 2 mA
01: 4 mA
10: 6 mA
11: 8 mA
R/W
D6
MS1_SRC
R/W
D5
Preliminary Rev. 0.95
CLK1_INV
R/W
D4
Function
CLK1_SRC[1:0]
D3
R/W
D2
Si5351A/B/C
CLK1_IDRV[1:0]
D1
R/W
D0
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