Si5351A-A-GM Silicon Laboratories Inc, Si5351A-A-GM Datasheet - Page 23

• Manufacturer Part Number: Si5351A-A-GM
• Description: Clock Generators & Support Products AnyRate 2 PLL 125MHz Clk&I2C 8out
• Manufacturer: Silicon Laboratories Inc
• Type: Any Frequency CMOS Clock Generatorr

Specifications of Si5351A-A-GM

• Mounting Style: SMD/SMT
• Max Input Freq: 0.008 MHz
• Max Output Freq: 133 MHz
• Number Of Outputs: 8
• Operating Supply Voltage: 3.3 V
• Operating Temperature Range: - 40 C to + 85 C
• Supply Current: 25 mA
• Package / Case: QFN-20
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Register
7. Register Map Summary
The following is a summary of the register map used to read status, control, and configure the Si5351.
10–14
26–41
4–8
15
16
17
18
19
20
21
22
23
24
25
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
0
1
2
3
9
OEB_CLK7
CLK0_PDN
CLK1_PDN
CLK2_PDN
CLK3_PDN
CLK4_PDN
CLK5_PDN
CLK6_PDN
CLK7_PDN
SYS_INIT
SYSCAL_
SYSCAL_
CLK7_EN
MASK
STKY
CLK3_DIS_STATE
CLK7_DIS_STATE
7
0
OEB_CLK6
CLK6_EN
MS0_INT
MS1_INT
MS2_INT
MS3_INT
MS4_INT
MS5_INT
FBA_INT
FBB_INT
LOS_B_
LOS_B_
LOL_B
MASK
STKY
MS0_P3[19:16]
MS1_P3[19:16]
MS2_P3[19:16]
6
0
Use ClockBuilder Desktop Software to Determine These Register Values.
PLL, MultiSynth, and output clock delay offset Configuration Registers.
R0_DIV[2:0]
R1_DIV[2:0]
R2_DIV[2:0]
OEB_CLK5
MS0_SRC
MS1_SRC
MS2_SRC
MS3_SRC
MS4_SRC
MS5_SRC
MS6_SRC
MS6_SRC
CLK5_EN
LOL_A _
LOL_A_
LOL_A
MASK
STKY
CLK2_DIS_STATE
CLK6_DIS_STATE
5
0
Preliminary Rev. 0.95
OEB_CLK4
CLK0_INV
CLK1_INV
CLK2_INV
CLK3_INV
CLK4_INV
CLK5_INV
CLK6_INV
CLK7_INV
CLK4_EN
MASK
LOS_
STKY
LOS_
LOS
4
0
MS0_P3[15:8]
MS0_P1[15:8]
MS0_P2[15:8]
MS1_P3[15:8]
MS1_P1[15:8]
MS1_P2[15:8]
MS2_P3[15:8]
MS2_P1[15:8]
MS2_P2[15:8]
MS0_P3[7:0]
MS0_P1[7:0]
MS0_P2[7:0]
MS1_P3[7:0]
MS1_P1[7:0]
MS1_P2[7:0]
MS2_P3[7:0]
MS2_P1[7:0]
MS2_P2[7:0]
Reserved
Reserved
OEB_CLK3
PLLB_SRC
CLK3_EN
3
CLK1_DIS_STATE
CLK5_DIS_STATE
CLK0_SRC[1:0]
CLK1_SRC[1:0]
CLK2_SRC[1:0]
CLK3_SRC[1:0]
CLK4_SRC[1:0]
CLK5_SRC[1:0]
CLK6_SRC[1:0]
CLK7_SRC[1:0]
OEB_CLK2
PLLA_SRC
CLK2_EN
2
MS0_P2[19:16]
MS1_P2[19:16]
MS2_P2[19:16]
Si5351A/B/C
OEB_CLK1
CLK1_EN
CLK0_DIS_STATE
CLK4_DIS_STATE
1
0
CLK6_IDRV[1:0]
CLK7_IDRV[1:0]
CLK0_IDRV[1:0]
CLK1_IDRV[1:0]
CLK2_IDRV[1:0]
CLK3_IDRV[1:0]
CLK4_IDRV[1:0]
CLK5_IDRV[1:0]
MS0_P1[17:16]
MS1_P1[17:16]
MS2_P1[17:16]
REVID[1:0]
OEB_CLK0
CLK0_EN
0
0
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