NCN6001DTBR2G ON Semiconductor, NCN6001DTBR2G Datasheet - Page 5

• Manufacturer Part Number: NCN6001DTBR2G
• Description: IC INTERFACE SMART CARD 20TSSOP
• Manufacturer: ON Semiconductor

Specifications of NCN6001DTBR2G

• Applications: Smart Card
• Interface: Microcontroller
• Voltage - Supply: 2.75 V ~ 5.5 V
• Package / Case: 20-TSSOP
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 25 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: NCN6001DTBR2GOS; NCN6001DTBR2GOS; NCN6001DTBR2GOSTR

PIN FUNCTIONS AND DESCRIPTION
TSSOP
10
11
12
13
14
15
16
17
LLGA
10
11
12
13
14
7
8
9
PWR_GND
CRD_VCC
CRD_CLK
Lout_H
Lout_L
Name
C8/S1
C4/S0
GND
OUTPUT
POWER
POWER
POWER
POWER
SIGNAL
Type
I/O
I/O
NOTE:
NOTE:
The Low Side of the external inductor is connected between this pin and pin 12 to
provide the DC/DC function. The current flowing into this inductor is internally sensed
and no external shunt resistor is used. Typically, Lout = 22 mH, with DSR < 2.0 W,
yields a good efficiency performance for a maximum 65 mA DC output load.
Note: The inductor shall be sized to handle the 450 mA peak current flowing during
the DC/DC operation (see CoilCraft manufacturer data sheet).
This pin is the Power Ground associated with the built−in DC/DC converter and must
be connected to the system ground together with GROUND pin 16. Using good quality
ground plane is recommended to avoid spikes on the logic signal lines.
The High Side of the external inductor is connected between this pin and pin 10 to
activate the DC/DC function. The built−in NMOS and PMOS devices provide the
switching function together with the CRD_VCC voltage rectification (Figure 17).
This pin provides the power to the external card. It is the logic level “1” for CRD_IO,
CRD_RST, CRD_C4, CRD_C8 and CRD_CLK signals.
The energy stored by the DC/DC external inductor Lout must be smoothed by a
10 mF/Low ESR capacitor, connected across CRD_VCC and GND. Using ceramic
type of capacitor (MURATA X5R, ESR < 50 mW) is strongly recommended. In the
event of a CRD_VCC U
feedback the information in the STATUS bit. The device does not take any further
action, particularly the DC/DC converter is neither stopped nor re programmed by the
NCN6001. It is up to the external MPU to handle the situation.
However, when the CRD_VCC is overloaded, the NCN6001 shuts off the DC/DC
converter, runs a Power Down ISO sequence and reports the fault in the STATUS
register.
Since high transient current flows from this pin to the load, care must be observed, at
PCB level, to minimize the series ESR and ESL parasitic values. The NCN6001 demo
board provides an example of a preferred PCB layout.
Auxiliary mixed analog/digital line to handle either a synchronous card, or as Chip
Select Identification (MISO, Bit 0): see Figure 9. The pin is driven by an open drain
stage, the pullup resistor being connected to the CRD_VCC supply. When the pin is
used as a logic input (asynchronous cards), the positive logic condition applies:
A built−in accelerator circuit makes sure the output positive going rise time is fully
within the ISO/EMV specifications.
Auxiliary mixed analog/digital line to handle either a synchronous card, or as Chip
Select Identification (MISO, Bit 1): see Figure 9. The pin is driven by an open drain
stage, the pullup resistor being connected to the CRD_VCC supply. When the pin is
used as a logic input (asynchronous cards), the positive logic condition applies:
A built−in accelerator circuit makes sure the output positive going rise time is fully
within the ISO/EMV specifications.
The logic and low level analog signals shall be connected to this ground pin. This pin
must be externally connected to the PWR_GND pin 12. The designer must make sure
no high current transients are shared with the low signal currents flowing into this pin.
This pin is connected to the CLK pin of the card connector. The CRD_CLK signal
comes from the clock selector circuit output. An internal active pull down NMOS device
forces this pin to Ground during either the CRD_VCC startup sequence, or when
CRD_VCC = 0 V.
The rise and fall slopes, either FAST or SLOW, of this signal can be programmed by
the MOSI message (Table 2).
Care must be observed, at PCB level, to minimize the pick−up noise coming from the
CRD_CLK line.
http://onsemi.com
The pin is capable of reading the logic level when the chip operates an
asynchronous interface, but is not intended to read the data from the
external card when operated in the synchronous mode. It merely returns the
logic state forced during a write instruction to the card.
The pin is capable of reading the logic level when the chip operates an
asynchronous interface, but is not intended to read the data from the
external card when operated in the synchronous mode. It merely returns the
logic state forced during a write instruction to the card.
Connected to GND → Logic = Zero
Connected to V
Connected to GND → Logic = Zero
Connected to V
5
VLOW
CC
CC
or left Open → Logic = One
or left Open → Logic = One
voltage, the NCN6001 detects the situation and
Description