NCN6001DTBR2G ON Semiconductor, NCN6001DTBR2G Datasheet - Page 13

• Manufacturer Part Number: NCN6001DTBR2G
• Description: IC INTERFACE SMART CARD 20TSSOP
• Manufacturer: ON Semiconductor

Specifications of NCN6001DTBR2G

• Applications: Smart Card
• Interface: Microcontroller
• Voltage - Supply: 2.75 V ~ 5.5 V
• Package / Case: 20-TSSOP
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 25 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: NCN6001DTBR2GOS; NCN6001DTBR2GOS; NCN6001DTBR2GOSTR

Read Register " READ_REG
interface and from the external card. The selected register is
transferred to the MISO pin during the MOSI sequence
(CS = Low). Table 3 gives the bits definition.
content of READ_REG is transferred on the MISO line
ASYNCHRONOUS MODE
define the physical addresses of the interfaces when a bank
of up to four NCN6001 share the same digital bus.
SYNCHRONOUS MODE
smart card and it is no longer possible to share the CS signal
with other device. Consequently, a dedicated Chip Select
signal must be provided when the interfaces operate in a
multiple operation mode (Figure 34).
register contain the smart card data, programming the
Example:
Table 3. MOSI and MISO Bits Identifications and Functions
The READ_REG register contains the data read from the
Depending upon the programmed SPI_MODE, the
In this mode, the CRD_C4 and CRD_C8 pins are used to
In this mode, CRD_C4 and CRD_C8 are connected to the
On the other hand, since bits [b4 – b0] of the MOSI
MOSI
MISO
b7
0
0
0
0
1
1
z
LDAA #%10010111
STAA MOSI
LDAA #%11010011
STAA MOSI
LDAA #%00111110
STAA MOSI
b6
0
0
1
1
0
1
z
b5
0
1
0
1
0
0
z
Card Detect
RST
RST
RST
RST
RST
RST
b4
CLK
CLK
CLK
CLK
CLK
CLK
I/O
b3
http://onsemi.com
CLK
CLK
CLK
CLK
CLK
I/O
C4
b2
;set RST = H, CLK = 1/1, VCC = 5.0 V
;SYNC. Card: set RST = H, CLK = L, IO = L, C4 = H, C8= H
;ASYNC. Card: set RST = H, CLK = ¼, VCC = 3.0 V
13
V
V
V
V
V
C4
C8
b1
CC
CC
CC
CC
CC
either on the Positive going (SPI_MODE = Special) or upon
the Negative going slope (SPI_MODE = Normal) of the
CLK_SPI signal. The external microcontroller shall discard
the three high bytes since they carry no valid data.
CRD_VCC output voltage shall be done by sending a
previous MOSI message according to Table 1 and Table 2.
WRT_REG[b4] during the chip programming sequence.
Since this bit shall be Low to address the internal register of
the chip, care must be observed as this signal will be
immediately transferred to the CRD_RST pin.
in this mode, the MOSI register must use the format
%100XXXXX to program the chip (%100 prefix, XXXXX
data).
The CRD_RST pin reflects the content of the MOSI
Since no physical address can exist when the chip operates
PWR Monitor
V
V
V
V
V
C8
b0
CC
CC
CC
CC
CC
Asynchronous, Program Chip
Asynchronous, Program Chip
Asynchronous, Program Chip
Asynchronous, Program Chip
Asynchronous, Program Chip
Synchronous, Sets Card Bits
Read Back Data
Operating Mode