AS3930-BQFT austriamicrosystems, AS3930-BQFT Datasheet - Page 21

• Manufacturer Part Number: AS3930-BQFT
• Description: IC RF PROGRAM RECEIVER 16-QFN
• Manufacturer: austriamicrosystems

Specifications of AS3930-BQFT

• Rf Type: Read / Write
• Frequency: 110kHz ~ 150kHz
• Features: RSSI Equipped
• Package / Case: 16-VFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: AS3930-BQFTTR

AS3930
Data Sheet - D e t a i l e d D e s c r i p t i o n
Table 18. Bit Rate Setup
If the preamble is detected correctly the correlator keeps searching for a data pattern. The duration of the preamble plus the pattern should not
be longer than 40 bits (see bit rate definition in
in the registers R5<7:0> and R6<7:0>. The two bytes define the pattern consisting of 16 half bit periods. This means the pattern and the bit
period can be selected by the user. The only limitation is that the pattern (in combination with preamble) must obey Manchester coding and
timing. It must be noted that according to Manchester coding a down-to-up bit transition represents a symbol "0", while a transition up-to-down
represents a symbol "1". If the default code is used (96 [hex]) the binary code is (10 01 01 10 01 10 10 01). MSB has to be transmitted first.
The user can also select (R1<2>) if single or double data pattern is used for wake-up. In case double pattern detection is set, the same pattern
has to be repeated 2 times.
Additionally it is possible to set the number of allowed missing zero bits (not symbols) in the received bitstream (R2<6:5>), as shown in the
19.
Table 19. Allowed Pattern Detection Errors
If the pattern is matched the wake-up interrupt is displayed on the WAKE output. In case the Manchester decoder is enabled (R1<3>) the data
coming out from the DAT pin are decoded and the clock is recovered on the pin DAT_CL.
The data coming out from the DAT pin are stable (and therefore can be acquired) on the rising edge of the CL_DAT clock, as shown in
www.austriamicrosystems.com/AS3930
R7<4>
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
R2<6>
R7<3>
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
R7<2>
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
R7<1>
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Table
R7<0>
R2<5>
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
18). The data pattern can be defined by the user and consists of two bytes which are stored
Bit duration in RTC
clock periods
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Revision 1.0
Maximum allowed error in the pattern detection
Bit rate (bits/s)
2184
2048
1926
1820
1724
1638
1560
1488
1424
1364
1310
1260
1212
1170
1128
1092
1056
1024
No error allowed
2 missed zeros
3 missed zeros
1 missed zero
Symbol rate (Manchester
symbols/s)
1092
1024
963
910
862
819
780
744
712
682
655
630
606
585
564
546
528
512
Figure
21 - 33
Table
16.