SI1015-A-GM Silicon Laboratories Inc, SI1015-A-GM Datasheet - Page 158

• Manufacturer Part Number: SI1015-A-GM
• Description: IC TXRX MCU + EZRADIOPRO
• Manufacturer: Silicon Laboratories Inc

Specifications of SI1015-A-GM

• Package / Case: 42-QFN
• Frequency: 240MHz ~ 960MHz
• Data Rate - Maximum: 256kbps
• Modulation Or Protocol: FSK, GFSK, OOK
• Applications: General Purpose
• Power - Output: 13dBm
• Sensitivity: -121dBm
• Voltage - Supply: 0.9 V ~ 3.6 V
• Current - Receiving: 18.5mA
• Current - Transmitting: 30mA
• Data Interface: PCB, Surface Mount
• Memory Size: 8kB Flash, 768B RAM
• Antenna Connector: PCB, Surface Mount
• Number Of Receivers: 1
• Number Of Transmitters: 1
• Wireless Frequency: 240 MHz to 960 MHz
• Interface Type: UART, SMBus, SPI, PCA
• Output Power: 13 dBm
• Operating Supply Voltage: 0.9 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Maximum Supply Current: 4 mA
• Minimum Operating Temperature: - 40 C
• Modulation: FSK, GFSK, OOK
• Protocol Supported: C2, SMBus
• Core: 8051
• Program Memory Type: Flash
• Program Memory Size: 8 KB
• Data Ram Size: 768 B
• Supply Current (max): 4 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1868-5

Si1010/1/2/3/4/5
14.1. Normal Mode
The MCU is fully functional in Normal Mode. Figure 14.1 shows the on-chip power distribution to various
peripherals. There are three supply voltages powering various sections of the chip: VBAT,
VDD_MCU/DC+, and the 1.8 V internal core supply. VREG0, PMU0 and the SmaRTClock are always pow-
ered directly from the VBAT pin. All analog peripherals are directly powered from the VDD_MCU/DC+ pin,
which is an output in one-cell mode and an input in two-cell mode. All digital peripherals and the CIP-51
core are powered from the 1.8 V internal core supply. The RAM is also powered from the core supply in
Normal mode.
14.2. Idle Mode
Setting the Idle Mode Select bit (PCON.0) causes the CIP-51 to halt the CPU and enter Idle mode as soon
as the instruction that sets the bit completes execution. All internal registers and memory maintain their
original data. All analog and digital peripherals can remain active during Idle mode.
Note: To ensure the MCU enters a low power state upon entry into Idle Mode, the one-shot circuit should be
Idle mode is terminated when an enabled interrupt is asserted or a reset occurs. The assertion of an
enabled interrupt will cause the Idle Mode Selection bit (PCON.0) to be cleared and the CPU to resume
operation. The pending interrupt will be serviced and the next instruction to be executed after the return
from interrupt (RETI) will be the instruction immediately following the one that set the Idle Mode Select bit.
If Idle mode is terminated by an internal or external reset, the CIP-51 performs a normal reset sequence
and begins program execution at address 0x0000.
158
enabled by clearing the BYPASS bit (FLSCL.6).
VBAT
SmaRTClock
PMU0
One-cell: 0.9 to 3.6 V
Two-cell: 1.8 to 3.6 V
Idle/Stop/Suspend
One-Cell Active/
One-Cell Sleep
DC0
Figure 14.1. Si1010/1/2/3/4/5 Power Distribution
Sleep
typical
1.9 V
Stop/Suspend
Active/Idle/
VDD_MCU/
RAM
DC+
VREG0
Rev. 1.0
1.8 V
Note: VDD_MCU/DC+ must be > VBAT
One-cell or Two-cell: 1.8 to 3.6 V
M
U
A
X
Analog Peripherals
CIP-51
Digital Peripherals
Core
SENSOR
TEMP
VREF
ADC
Timers
Flash
+
-
COMPARATORS
IREF0
VOLTAGE
SMBus
UART
SPI
+
-
GPIO