SI1015-A-GM Silicon Laboratories Inc, SI1015-A-GM Datasheet - Page 114
SI1015-A-GM
Manufacturer Part Number
SI1015-A-GM
Description
IC TXRX MCU + EZRADIOPRO
Manufacturer
Silicon Laboratories Inc
Specifications of SI1015-A-GM
Package / Case
42-QFN
Frequency
240MHz ~ 960MHz
Data Rate - Maximum
256kbps
Modulation Or Protocol
FSK, GFSK, OOK
Applications
General Purpose
Power - Output
13dBm
Sensitivity
-121dBm
Voltage - Supply
0.9 V ~ 3.6 V
Current - Receiving
18.5mA
Current - Transmitting
30mA
Data Interface
PCB, Surface Mount
Memory Size
8kB Flash, 768B RAM
Antenna Connector
PCB, Surface Mount
Number Of Receivers
1
Number Of Transmitters
1
Wireless Frequency
240 MHz to 960 MHz
Interface Type
UART, SMBus, SPI, PCA
Output Power
13 dBm
Operating Supply Voltage
0.9 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Maximum Supply Current
4 mA
Minimum Operating Temperature
- 40 C
Modulation
FSK, GFSK, OOK
Protocol Supported
C2, SMBus
Core
8051
Program Memory Type
Flash
Program Memory Size
8 KB
Data Ram Size
768 B
Supply Current (max)
4 mA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Operating Temperature
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1868-5
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
SI1015-A-GM
Manufacturer:
Silicon Labs
Quantity:
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Part Number:
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Si1010/1/2/3/4/5
8. CIP-51 Microcontroller
The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the
MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop soft-
ware. The MCU family has a superset of all the peripherals included with a standard 8051. The CIP-51
also includes on-chip debug hardware (see description in Section 29), and interfaces directly with the ana-
log and digital subsystems providing a complete data acquisition or control-system solution in a single inte-
grated circuit.
The CIP-51 Microcontroller core implements the standard 8051 organization and peripherals as well as
additional custom peripherals and functions to extend its capability (see Figure 8.1 for a block diagram).
The CIP-51 includes the following features:
8.1. Performance
The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the stan-
dard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system
clock cycles to execute, and usually have a maximum system clock of 12 MHz. By contrast, the CIP-51
core executes 70% of its instructions in one or two system clock cycles, with no instructions taking more
than eight system clock cycles.
114
Fully Compatible with MCS-51 Instruction Set
25 MIPS Peak Throughput with 25 MHz Clock
0 to 25 MHz Clock Frequency
Extended Interrupt Handler
RESET
CLOCK
STOP
IDLE
Figure 8.1. CIP-51 Block Diagram
ACCUMULATOR
PROGRAM COUNTER (PC)
CONTROL
PSW
PRGM. ADDRESS REG.
LOGIC
POWER CONTROL
PC INCREMENTER
DATA POINTER
REGISTER
BUFFER
TMP1
PIPELINE
ALU
Rev. 1.0
TMP2
DATA BUS
DATA BUS
D8
D8
D8
A16
D8
D8
D8
D8
B REGISTER
Reset Input
Power Management Modes
On-chip Debug Logic
Program and Data Memory Security
REGISTER
INTERFACE
INTERFACE
INTERRUPT
INTERFACE
ADDRESS
MEMORY
SRAM
SFR
BUS
MEM_WRITE_DATA
SFR_WRITE_DATA
MEM_READ_DATA
STACK POINTER
SFR_READ_DATA
SRAM
MEM_ADDRESS
MEM_CONTROL
EMULATION_IRQ
SFR_ADDRESS
SFR_CONTROL
SYSTEM_IRQs
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