XC56309VL100A Freescale Semiconductor, XC56309VL100A Datasheet - Page 32

• Manufacturer Part Number: XC56309VL100A
• Description: IC DSP 24BIT 100MHZ 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: DSP563xxr
• Type: Fixed Pointr

Specifications of XC56309VL100A

• Interface: Host Interface, SSI, SCI
• Clock Rate: 100MHz
• Non-volatile Memory: ROM (576 B)
• On-chip Ram: 24kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 196-MAPBGA
• Device Core Size: 24b
• Format: Fixed Point
• Clock Freq (max): 100MHz
• Mips: 100
• Device Input Clock Speed: 100MHz
• Ram Size: 102KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Signals/Connections
2.6 Interrupt and Mode Control
The interrupt and mode control signals select the chip’s operating mode as it comes out of
hardware reset. After
2-8
Signal Name
RESET
MODA/IRQA
MODB/IRQB
Input
Input
Input
Type
Input
Input
Input
During
RESET
Reset
State
Table 2-9. Interrupt and Mode Control
is deasserted, these inputs are hardware interrupt request lines.
Reset
Deassertion of RESET is internally synchronized to the clock out (CLKOUT). When
asserted, the chip is placed in the Reset state and the internal phase generator is
reset. The Schmitt-trigger input allows a slowly rising input (such as a capacitor
charging) to reset the chip reliably. If RESET is deasserted synchronous to CLKOUT,
exact start-up timing is guaranteed, allowing multiple processors to start and operate
synchronously. When the RESET signal is deasserted, the initial chip operating mode
is latched from the MODA, MODB, MODC, and MODD inputs. The RESET signal
must be asserted after power-up.
RESET can tolerate 5 V.
Mode Select A/External Interrupt Request A
Selects the initial chip operating mode during hardware reset and becomes a
level-sensitive or negative-edge-triggered, maskable interrupt request input during
normal instruction processing. MODA/IRQA MODA, MODB, MODC, and MODD select
one of sixteen initial chip operating modes, latched into the OMR when the RESET
signal is deasserted.
Internally synchronized to CLKOUT. If IRQA is asserted synchronous to CLKOUT,
multiple processors can be re-synchronized using the WAIT instruction and asserting
IRQA to exit the Wait state. If a STOP instruction puts the processor is in the Stop
standby state and IRQA is asserted, the processor exits the Stop state.
MODA
Mode Select B/External Interrupt Request B
Selects the initial chip operating mode during hardware reset and becomes a
level-sensitive or negative-edge-triggered, maskable interrupt request input during
normal instruction processing. MODA, MODB, MODC, and MODD select one of
sixteen initial chip operating modes, latched into OMR when the RESET signal is
deasserted.
Internally synchronized to CLKOUT. If IRQB is asserted synchronous to CLKOUT,
multiple processors can be re-synchronized using the WAIT instruction and asserting
IRQB to exit the Wait state.
MODB/IRQB can tolerate 5 V.
DSP56309 User’s Manual, Rev. 1
/IRQA can tolerate 5 V.
Signal Description
Freescale Semiconductor