XC56309VL100A Freescale Semiconductor, XC56309VL100A Datasheet - Page 216

• Manufacturer Part Number: XC56309VL100A
• Description: IC DSP 24BIT 100MHZ 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: DSP563xxr
• Type: Fixed Pointr

Specifications of XC56309VL100A

• Interface: Host Interface, SSI, SCI
• Clock Rate: 100MHz
• Non-volatile Memory: ROM (576 B)
• On-chip Ram: 24kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 196-MAPBGA
• Device Core Size: 24b
• Format: Fixed Point
• Clock Freq (max): 100MHz
• Mips: 100
• Device Input Clock Speed: 100MHz
• Ram Size: 102KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Triple Timer Module
9.4.4 Timer Control/Status Register (TCSR)
The TCSR is a read/write register controlling the timer and reflecting its status.
9-24
Bit Number
DIR
23
11
23–22
19–16
21
20
15
14
Reserved. Read as 0. Write to 0 for future compatibility
22
10
Bit Name
Table 9-3. Timer Control/Status Register (TCSR) Bit Definitions
TOF
PCE
TCF
TRM
TCF
21
9
Figure 9-23. Timer Control/Status Register (TCSR)
TOF
INV
Reset Value
20
8
0
0
0
0
0
0
TC3
19
7
DSP56309 User’s Manual, Rev. 1
Reserved. Write to zero for future compatibility.
Timer Compare Flag
Indicate that the event count is complete. In timer, PWM, and watchdog
modes, the TCF bit is set after (M – N + 1) events are counted. (M is the
value in the compare register and N is the TLR value.) In measurement
modes, the TCF bit is set when the measurement completes. Writing a one to
the TCF bit clears it. A zero written to the TCF bit has no effect. The bit is also
cleared when the timer compare interrupt is serviced. The TCF bit is cleared
by a hardware RESET signal, a software RESET instruction, the STOP
instruction, or by clearing the TCSR[TE] bit to disable the timer.
Note:
Timer Overflow Flag
Indicates that a counter overflow has occurred. This bit is cleared by writing a
one to the TOF bit. Writing a zero to TOF has no effect. The bit is also cleared
when the timer overflow interrupt is serviced. The TOF bit is cleared by a
hardware RESET signal, a software RESET instruction, the STOP
instruction, or by clearing the TCSR[TE] bit to disable the timer
Reserved. Write to zero for future compatibility.
Prescaler Clock Enable
Selects the prescaler clock as the timer source clock. When PCE is cleared,
the timer uses either an internal (CLK/2) signal or an external (TIO) signal as
its source clock. When PCE is set, the prescaler output is the timer source
clock for the counter, regardless of the timer operating mode. To ensure
proper operation, the PCE bit is changed only when the timer is disabled. The
PS[1–0] bits of the TPLR determine which source clock is used for the
prescaler. A timer can be clocked by a prescaler clock that is derived from the
TIO of another timer.
Reserved. Write to zero for future compatibility.
TC2
18
6
The TOF and TCF bits are cleared by a 1 written to the specific bit.
To ensure that only the target bit is cleared, do not use the BSET
command. The proper way to clear these bits is to write 1, using a
MOVEP instruction, to the flag to be cleared and 0 to the other flag.
TC1
17
5
TC0
16
4
Description
PCE
15
3
TCIE
14
2
TOIE
Freescale Semiconductor
DO
13
1
.
TE
12
DI
0