HD64F3048BF25 Renesas Electronics America, HD64F3048BF25 Datasheet - Page 17

• Manufacturer Part Number: HD64F3048BF25
• Description: IC H8 MCU FLASH 128K 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3048BF25

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

4.3
4.4
4.5
4.6
Section 5 Interrupt Controller
5.1
5.2
5.3
5.4
5.5
Section 6 Bus Controller
6.1
6.2
Interrupts ........................................................................................................................... 88
Trap Instruction................................................................................................................. 89
Stack Status after Exception Handling.............................................................................. 89
Notes on Stack Usage ....................................................................................................... 90
Overview........................................................................................................................... 91
5.1.1
5.1.2
5.1.3
5.1.4
Register Descriptions ........................................................................................................ 94
5.2.1
5.2.2
5.2.3
5.2.4
5.2.5
Interrupt Sources............................................................................................................... 105
5.3.1
5.3.2
5.3.3
Interrupt Operation............................................................................................................ 111
5.4.1
5.4.2
5.4.3
Usage Notes ...................................................................................................................... 118
5.5.1
5.5.2
5.5.3
5.5.4
5.5.5
Overview........................................................................................................................... 123
6.1.1
6.1.2
6.1.3
6.1.4
Register Descriptions ........................................................................................................ 126
6.2.1
6.2.2
Features................................................................................................................ 91
Block Diagram ..................................................................................................... 92
Pin Configuration................................................................................................. 93
Register Configuration......................................................................................... 93
System Control Register (SYSCR) ...................................................................... 94
Interrupt Priority Registers A and B (IPRA, IPRB)............................................. 95
IRQ Status Register (ISR).................................................................................... 102
IRQ Enable Register (IER) .................................................................................. 103
IRQ Sense Control Register (ISCR) .................................................................... 104
External Interrupts ............................................................................................... 105
Internal Interrupts................................................................................................. 107
Interrupt Vector Table.......................................................................................... 107
Interrupt Handling Process................................................................................... 111
Interrupt Sequence ............................................................................................... 116
Interrupt Response Time...................................................................................... 117
Contention between Interrupt and Interrupt-Disabling Instruction ...................... 118
Instructions That Inhibit Interrupts ...................................................................... 119
Interrupts during EEPMOV Instruction Execution.............................................. 119
Usage Notes on External Interrupts ..................................................................... 119
Notes on Non-Maskable Interrupts (NMI)........................................................... 121
Features................................................................................................................ 123
Block Diagram ..................................................................................................... 124
Input/Output Pins ................................................................................................. 125
Register Configuration......................................................................................... 126
Bus Width Control Register (ABWCR)............................................................... 126
Access State Control Register (ASTCR) ............................................................. 127
................................................................................................... 123
.......................................................................................... 91
Rev. 3.00 Sep 27, 2006 page xv of xxvi