C8051F311 Silicon Laboratories Inc, C8051F311 Datasheet - Page 206

IC 8051 MCU 16K FLASH 28MLP

C8051F311

Manufacturer Part Number
C8051F311
Description
IC 8051 MCU 16K FLASH 28MLP
Manufacturer
Silicon Laboratories Inc
Series
C8051F31xr
Datasheets

Specifications of C8051F311

Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
25
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 17x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
C8051F311-GM
Manufacturer:
SILICONLABS/芯科
Quantity:
20 000
Part Number:
C8051F311-GMR
Manufacturer:
SILICON LABS/芯科
Quantity:
20 000
Part Number:
C8051F311-GMR
0
Company:
Part Number:
C8051F311-GMR
Quantity:
441
C8051F310/1/2/3/4/5/6/7
18.2.1. Edge-triggered Capture Mode
In this mode, a valid transition on the CEXn pin causes the PCA to capture the value of the PCA counter/
timer and load it into the corresponding module's 16-bit capture/compare register (PCA0CPLn and
PCA0CPHn). The CAPPn and CAPNn bits in the PCA0CPMn register are used to select the type of transi-
tion that triggers the capture: low-to-high transition (positive edge), high-to-low transition (negative edge),
or either transition (positive or negative edge). When a capture occurs, the Capture/Compare Flag (CCFn)
in PCA0CN is set to logic 1 and an interrupt request is generated if CCF interrupts are enabled. The CCFn
bit is not automatically cleared by hardware when the CPU vectors to the interrupt service routine, and
must be cleared by software. If both CAPPn and CAPNn bits are set to logic 1, then the state of the Port
pin associated with CEXn can be read directly to determine whether a rising-edge or falling-edge caused
the capture.
Note: The CEXn input signal must remain high or low for at least 2 system clock cycles in order to be valid.
206
Port I/O
Crossbar
Figure 18.4. PCA Capture Mode Diagram
CEXn
W
P
M
1
6
n
x
PCA0CPMn
O
M
E
C
n
0
Rev. 1.7
C
A
P
P
n
C
A
P
N
n
0
1
M
A
T
n
x 0 0 x
T
O
G
n
W
M
P
n
E
C
C
F
n
0
1
C
F
C
R
PCA0CN
C
C
F
4
C
C
F
3
PCA
Timebase
C
C
F
2
C
C
F
1
PCA Interrupt
C
C
F
0
Capture
PCA0CPLn
PCA0L
PCA0CPHn
PCA0H

Related parts for C8051F311