MC9S08GB60CFU Freescale Semiconductor, MC9S08GB60CFU Datasheet - Page 164

• Manufacturer Part Number: MC9S08GB60CFU
• Description: IC MCU 60K FLASH 20MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08GB60CFU

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• For Use With: M68DEMO908GB60E - BOARD DEMO MC9S08GB60M68EVB908GB60E - BOARD EVAL FOR MC9S08GB60
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Timer/PWM (TPM) Module
CHnF — Channel n Flag
CHnIE — Channel n Interrupt Enable
MSnB — Mode Select B for TPM Channel n
MSnA — Mode Select A for TPM Channel n
164
When channel n is configured for input capture, this flag bit is set when an active edge occurs on the
channel n pin. When channel n is an output compare or edge-aligned PWM channel, CHnF is set when
the value in the TPM counter registers matches the value in the TPM channel n value registers. This
flag is seldom used with center-aligned PWMs because it is set every time the counter matches the
channel value register, which correspond to both edges of the active duty cycle period.
A corresponding interrupt is requested when CHnF is set and interrupts are enabled (CHnIE = 1). Clear
CHnF by reading TPMxCnSC while CHnF is set and then writing a 0 to CHnF. If another interrupt
request occurs before the clearing sequence is complete, the sequence is reset so CHnF would remain
set after the clear sequence was completed for the earlier CHnF. This is done so a CHnF interrupt
request cannot be lost by clearing a previous CHnF.
Reset clears the CHnF bit. Writing a 1 to CHnF has no effect.
This read/write bit enables interrupts from channel n. Reset clears the CHnIE bit.
When CPWMS = 0, MSnB = 1 configures TPM channel n for edge-aligned PWM mode. For a
summary of channel mode and setup controls, refer to
When CPWMS = 0 and MSnB = 0, MSnA configures TPM channel n for input capture mode or output
compare mode. Refer to
1 = Input capture or output compare event occurred on channel n.
0 = No input capture or output compare event occurred on channel n.
1 = Channel n interrupt requests enabled.
0 = Channel n interrupt requests disabled (use software polling).
Table 10-3
MC9S08GB/GT Data Sheet, Rev. 2.3
for a summary of channel mode and setup controls.
Table
10-3.
Freescale Semiconductor