AT90S2333-8AC Atmel, AT90S2333-8AC Datasheet - Page 43

• Manufacturer Part Number: AT90S2333-8AC
• Description: IC MCU 2K FLSH 8MHZ A/D 32TQFP
• Manufacturer: Atmel
• Series: AVR® 90Sr

Specifications of AT90S2333-8AC

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 20
• Program Memory Size: 2KB (1K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 6 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 32-TQFP, 32-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

•
These two bits control the SCK rate of the device configured as a master. SPR1 and SPR0 have no effect on the slave. The
relationship between SCK and the Oscillator Clock frequency f
Table 18. Relationship Between SCK and the Oscillator Frequency
SPI Status Register - SPSR
•
When a serial transfer is complete, the SPIF bit is set (one) and an interrupt is generated if SPIE in SPCR is set (one) and
global interrupts are enabled. If SS is an input and is driven low when the SPI is in master mode, this will also set the SPIF
flag. SPIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, the SPIF bit is
cleared by first reading the SPI status register with SPIF set (one), then accessing the SPI Data Register (SPDR).
•
The WCOL bit is set if the SPI data register (SPDR) is written during a data transfer. The WCOL bit (and the SPIF bit) are
cleared (zero) by first reading the SPI Status Register with WCOL set (one), and then accessing the SPI Data Register.
•
These bits are reserved bits in the AT90S2333/4433 and will always read as zero.
The SPI interface on the AT90S2333/4433 is also used for program memory and EEPROM downloading or uploading. See
page 78 for serial programming and verification.
SPI Data Register - SPDR
The SPI Data Register is a read/write register used for data transfer between the register file and the SPI Shift register.
Writing to the register initiates data transmission. Reading the register causes the Shift Register Receive buffer to be read.
Bit
$0E ($2E)
Read/Write
Initial value
Bit
$0F ($2F)
Read/Write
Initial value
Bits 1,0 - SPR1, SPR0: SPI Clock Rate Select 1 and 0
Bit 7 - SPIF: SPI Interrupt Flag
Bit 6 - WCOL: Write COLlision flag
Bit 5..0 - Res: Reserved bits
SPIF
MSB
SPR1
R/W
R
7
0
7
X
0
0
1
1
WCOL
R/W
R
X
6
0
6
R/W
R
X
5
0
5
-
R/W
R
4
0
4
X
-
AT90S/LS2333 and AT90S/LS4433
R/W
R
3
0
3
X
-
SPR0
0
1
0
1
cl
is shown in the following table:
R/W
R
X
2
0
2
-
R/W
R
X
1
0
1
-
LSB
R/W
R
X
0
0
0
-
Undefined
SCK Frequency
SPDR
SPSR
f
f
f
cl
f
cl
cl
cl
/
/
/
/
128
16
64
4
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