AT90S2333-8AC Atmel, AT90S2333-8AC Datasheet - Page 25

• Manufacturer Part Number: AT90S2333-8AC
• Description: IC MCU 2K FLSH 8MHZ A/D 32TQFP
• Manufacturer: Atmel
• Series: AVR® 90Sr

Specifications of AT90S2333-8AC

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 20
• Program Memory Size: 2KB (1K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 6 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 32-TQFP, 32-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Timer/Counter Interrupt Flag Register - TIFR
•
The TOV1 is set (one) when an overflow occurs in Timer/Counter1. TOV1 is cleared by hardware when executing the cor-
responding interrupt handling vector. Alternatively, TOV1 is cleared by writing a logic one to the flag. When the I-bit in
SREG, and TOIE1 (Timer/Counter1 Overflow Interrupt Enable), and TOV1 are set (one), the Timer/Counter1 Overflow
Interrupt is executed. In PWM mode, this bit is set when Timer/Counter1 advances from $0000.
•
The OCF1 bit is set (one) when compare match occurs between the Timer/Counter1 and the data in OCR1 - Output Com-
pare Register 1. OCF1 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively,
OCF1 is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE1 (Timer/Counter1 Compare match
InterruptA Enable), and the OCF1 are set (one), the Timer/Counter1 Compare match Interrupt is executed.
•
These bits are reserved bits in the AT90S2333/4433 and always read as 0.
•
The ICF1 bit is set (one) to flag an input capture event, indicating that the Timer/Counter1 value has been transferred to the
input capture register - ICR1. ICF1 is cleared by hardware when executing the corresponding interrupt handling vector.
Alternatively, ICF1 is cleared by writing a logic one to the flag. When the SREG I-bit, and TICIE1 (Timer/Counter1 Input
Capture Interrupt Enable), and ICF1 are set (one), the Timer/Counter1 Capture Interrupt is executed.
•
This bit is a reserved bit in the AT90S2333/4433 and always reads as 0.
•
The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the
corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logic one to the flag. When the SREG I-
bit, and TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set (one), the Timer/Counter0 Overflow interrupt
is executed.
•
This bit is a reserved bit in the AT90S2333/4433 and always reads as zero.
External Interrupts
The external interrupts are triggered by the INT1 and INT0 pins. Observe that, if enabled, the interrupts will trigger even if
the INT0/INT1 pins are configured as outputs. This feature provides a way of generating a software interrupt. The external
interrupts can be triggered by a falling or rising edge or a low level. This is set up as indicated in the specification for the
MCU Control Register - MCUCR. When the external interrupt is enabled and is configured as level triggered, the interrupt
will trigger as long as the pin is held low.
The external interrupts are set up as described in the specification for the MCU Control Register - MCUCR.
Interrupt Response Time
The interrupt execution response for all the enabled AVR interrupts is 4 clock cycles minimum. 4 clock cycles after the
interrupt flag has been set, the program vector address for the actual interrupt handling routine is executed. During this 4
clock cycle period, the Program Counter (2 bytes) is pushed onto the Stack, and the Stack Pointer is decremented by 2.
The vector is normally a relative jump to the interrupt routine, and this jump takes 2 clock cycles. If an interrupt occurs dur-
ing execution of a multi-cycle instruction, this instruction is completed before the interrupt is served.
A return from an interrupt handling routine (same as for a subroutine call routine) takes 4 clock cycles. During these 4 clock
cycles, the Program Counter (2 bytes) is popped back from the Stack, the Stack Pointer is incremented by 2, and the I flag
in SREG is set. When the AVR exits from an interrupt, it will always return to the main program and execute one more
instruction before any pending interrupt is served.
Bit
$38 ($58)
Read/Write
Initial value
Bit 7 - TOV1: Timer/Counter1 Overflow Flag
Bit 6 - OCF1: Output Compare Flag 1
Bit 5, 4 - Res: Reserved Bits
Bit 3 - ICF1: Input Capture Flag 1
Bit 2 - Res: Reserved Bit
Bit 1 - TOV0: Timer/Counter0 Overflow Flag
Bit 0 - Res: Reserved bit
TOV1
R/W
7
0
OCF1
R/W
6
0
R
5
0
-
R
4
0
-
AT90S/LS2333 and AT90S/LS4433
ICF1
R/W
3
0
R
2
0
-
TOV0
R/W
1
0
R
0
0
-
TIFR
25