DS80C390-QCR Maxim Integrated Products, DS80C390-QCR Datasheet - Page 5

• Manufacturer Part Number: DS80C390-QCR
• Description: IC MPU CAN DUAL HS 68-PLCC
• Manufacturer: Maxim Integrated Products
• Series: 80Cr

Specifications of DS80C390-QCR

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SIO, UART/USART
• Peripherals: Power-Fail Reset, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3.85 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 68-LCC, 68-PLCC
• Processor Series: DS80C390
• Core: 8051
• Data Bus Width: 8 bit
• Program Memory Size: 4 KB
• Data Ram Size: 4 KB
• Interface Type: CAN, IrDA
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Operating Supply Voltage: 3.85 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Note 12:
MOVX CHARACTERISTICS (MULTIPLEXED ADDRESS/DATA BUS) (Note 12)
MOVX ALE Pulse Width
Port 0 MOVX Address, CE0–4,
PCE0–4 Valid to ALE Low
Address Hold After MOVX
Read/Write
RD Pulse Width
WR Pulse Width
RD Low to Valid Data In
Data Hold After Read
Data Float After Read
ALE Low to Valid Data In
Port 0 Address, Port 4 CE, Port 5
PCE to Valid Data In
Port 2, 4 Address to Valid Data In
ALE Low to RD or WR Low
Port 0 Address, Port 4 CE, Port 5
PCE to RD or WR Low
Port 2, 4 Address to or WR Low
Data Valid to WR Transition
Data Hold After WR High
RD Low to Address Float
RD or WR High to ALE, Port 4 CE
or Port 5 PCE High
All parameters apply to both commercial and industrial temperature operation. C
1, 2 and 4 for one XTAL1 cycle prior to change in output address from Port 1, 2, and 4.
MD2:0 bits. t
except Port 0, ALE, PSEN, RD, and WR with 100pF. Interfacing to memory devices with float times over 25ns can cause bus
contention and an increase in operating current. Specifications assume a 50% duty cycle for the oscillator; port 2 and ALE timing
changes in relation to duty cycle variation. Some AC timing characteristic drawings show the CLK signal, provided to determine the
relative occurrence of events and not the timing of signals relative to the external clock. During the external addressing mode, weak
latches maintain the previously driven value from the processor on Port 0 until Port 0 is overdriven by external memory; and on Port
PARAMETER
MCS
is a time period shown in the t
SYMBOL
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
AVWL1
AVWL2
t
WLWH
t
AVDV1
AVDV2
AVLL2
LLAX2
LLAX3
QVWX
WHQX
WHLH
LHLL2
RHDX
RLRH
RLDV
RHDZ
LLWL
LLDV
RLAZ
MCS
0.375 t
2.625 t
C
C
0.625t
0.375 t
0.125 t
0.125 t
0.125 t
0.25 t
1.25 t
1.5 t
1.25 t
1.25 t
2.5 t
0.25 t
1.5 t
0.25 t
1.25 t
0.25t
ST
ST
0.25t
0.5t
0.5t
0.5 t
0.5 t
0.5 t
0.25t
Time Periods table. All signals characterized with load capacitance of 80pF
5 of 53
x t
x t
MIN
MCS
MCS
MCS
MCS
MCS
MCS
MCS
MCS
MCS
MCS
-8
-5
MCS
MCS
MCS
0
MCS
MCS
MCS
MCS
MCS
MCS
MCS
MCS
MCS
MCS
MCS
MCS
MCS
MCS
- 11
- 10
- 10
- 11
- 10
- 5
- 10
- 6
- 6
- 11
- 5
- 5
- 11
-5
- 5
- 10
- 10
- 5
- 11
- 7
- 11
- 8
- 7
- 5
- 5
- 5
- 5
(C
(C
(4C
(4C
(4C
(4C
ST
ST
ST
ST
ST
ST
0.125 t
0.625 t
C
1.25 t
0.75 t
0.75 t
0.25t
1.25 t
+ 0.25) x t
+ 1.25) x t
0.25 t
0.25 t
0.5 t
ST
See Note 12
1.5 t
+ 0.5) x t
+ 2.5) x t
+ 0.5) x t
+ 2.5) x t
0.5t
ST
x t
MAX
is the stretch cycle value determined by the
+10
MCS
MCS
MCS
MCS
MCS
MCS
MCS
MCS
MCS
MCS
MCS
MCS
MCS
- 20
+ 10
- 5
+ 10
- 5
+10
- 26
- 30
+ 10
+ 5
- 25
- 5
- 20
MCS
MCS
MCS
MCS
MCS
MCS
- 20
- 20
- 30
- 30
- 30
- 30
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
C
1 ≤ C
4 ≤ C
4 ≤ C
4 ≤ C
1 ≤ C
1 ≤ C
1 ≤ C
1 ≤ C
4 ≤ C
1 ≤ C
4 ≤ C
4 ≤ C
1 ≤ C
4 ≤ C
1 ≤ C
4 ≤ C
1 ≤ C
4 ≤ C
1 ≤ C
4 ≤ C
1 ≤ C
4 ≤ C
1 ≤ C
4 ≤ C
STRETCH
1≤ C
1≤ C
1≤ C
VALUES
ST
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
(MD2:0)
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
= 0
= 0
= 0
= 0
= 0
= 0
= 0
= 0
= 0
= 0
= 0
= 0
= 0
= 0
=0
≤ 3
≤ 3
≤ 3
≤ 3
≤ 7
≤ 7
≤ 7
≤ 7
≤ 7
≤ 7
≤ 3
≤ 7
≤ 3
≤ 7
≤ 7
≤ 3
≤ 7
≤ 3
≤ 7
≤ 3
≤ 7
≤ 3
≤ 7
≤ 3
≤ 7
≤ 3
≤ 7