MAXQ3108-FFN+ Maxim Integrated Products, MAXQ3108-FFN+ Datasheet - Page 59

• Manufacturer Part Number: MAXQ3108-FFN+
• Description: IC MCU DUAL-CORE 16BIT 28-TSSOP
• Manufacturer: Maxim Integrated Products
• Series: MAXQ™r

Specifications of MAXQ3108-FFN+

• Core Processor: RISC
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 11K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-TSSOP
• Processor Series: MAXQ
• Core: RISC
• Data Bus Width: 16 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, JTAG, SPI
• Maximum Clock Frequency: 10 MHz
• Number Of Programmable I/os: 22
• Number Of Timers: 2
• Operating Supply Voltage: 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

• AD0 to AD5: These six registers contain the most
• AD0LSB to AD5LSB: These six registers contain the
• ADCN: The ADC control register contains both con-
• ADCC: This register contains a measure of the clock
• MSTC: The Manchester decoder status register con-
Use Case: Using a Single DS8102 as a 2-Channel ADC
The DS8102 is designed to operate with the
Manchester data inputs of the MAXQ3108. Figure 4
demonstrates how simple the physical interface can be:
just connect the MNOUT pin of the DS8102 to the
Figure 4. Connecting the MAXQ3108 to a DS8102 Dual Delta-Sigma Modulator
significant 16 bits for the cubic sinc filters. AD0 and
AD1 correspond to Manchester decoder 0, AD2 and
AD3 correspond to Manchester decoder 1, and AD4
and AD5 correspond to Manchester decoder 2.
least significant 8 bits for the cubic sinc filters. Paired
with the AD0 to AD5 registers, each cubic sinc filter
has 24 bits of resolution.
trol bits and status bits associated with the ADC. The
register contains bits that configure the oversampling
rate, and enable or disable individual Manchester
decoder channels and interrupts and other functions.
rate associated with a particular Manchester
decoder. Because the speed of a Manchester chan-
nel is controlled not by the MAXQ3108 but by the
unsynchronized clock of an external device, it is criti-
cal for the application to know the difference
between the modulator clock and the MAXQ3108
clock. To determine this, the ADCC register contains
the number of sync bits that occur during 512
32.768kHz clock periods. Application software can
use this information to determine the relative speed
of the two clocks and to make correction for time-crit-
ical measurements.
tains bits that reveal the synchronization status of all
three Manchester decoders. It also contains the
selection bits for the clock measurement function
exposed in the ADCC register.
______________________________________________________________________________________
Low-Power, Dual-Core Microcontroller
AN0+
AN1+
AN0-
AN1-
ADC Registers
DS8102
MDIN0P input of the MAXQ3108, and establish a com-
mon ground using the MDIN0N pin. This interface point,
however, makes an ideal isolation interface. Because of
the Manchester-encoded nature of the signal interface,
any type of isolation—capacitive, transformer, or opti-
cal—can be used to couple the output of the DS8102 to
the MAXQ3108.
To use the ADC inputs, perform the following steps:
• Configure the ADC. In the ADCN register, set the
• Within a few milliseconds, the MD0SNC bit should go
• To read samples, wait for ABF0 to go active in the
The MAXQ3108 contains two MAXQ20 cores. The first
core, UserCore, operates at half the master clock
speed and manages most of the peripheral devices.
The second core, DSPCore, operates at the full master
clock speed and has no peripheral responsibility. It is
free to handle most of the math-intensive parts of the
application.
The DSPCore differs from the UserCore in two impor-
tant aspects: first, it has no debug engine; and second,
it has no nonvolatile program memory. Instead, the
MDIN0N
MDIN0P
OSR bits to select the desired oversampling rate,
either 32, 64, 128, or 256. Enable the Manchester
decoder 0 by setting MD0E.
active in the MSTC register. This indicates that the
synchronization pattern has been detected and that
samples in the AD0 register are valid.
ADCN register. This indicates that samples are avail-
able in the AD0 and AD1 registers. The sample input
loop can be as simple as:
while(TRUE)
{
}
while(!ADCN.ABF0);
process_sample(AD0);
MAXQ3108
Dual-Core Interfaces
59