MAXQ3108-FFN+ Maxim Integrated Products, MAXQ3108-FFN+ Datasheet - Page 44

• Manufacturer Part Number: MAXQ3108-FFN+
• Description: IC MCU DUAL-CORE 16BIT 28-TSSOP
• Manufacturer: Maxim Integrated Products
• Series: MAXQ™r

Specifications of MAXQ3108-FFN+

• Core Processor: RISC
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 11K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-TSSOP
• Processor Series: MAXQ
• Core: RISC
• Data Bus Width: 16 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, JTAG, SPI
• Maximum Clock Frequency: 10 MHz
• Number Of Programmable I/os: 22
• Number Of Timers: 2
• Operating Supply Voltage: 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Low-Power, Dual-Core Microcontroller
44
I2CIE (02h, 04h)
Initialization:
Read/Write Access:
I2CIE.0: I2CSRIE
I2CIE.1: I2CTXIE
I2CIE.2: I2CRXIE
I2CIE.3: I2CSTRIE
I2CIE.4: I2CTOIE
I2CIE.5: I2CAMIE
I2CIE.6: I2CALIE
I2CIE.7: I2CNACKIE
I2CIE.8: I2CGCIE
I2CIE.9: I2CROIE
I2CIE.10: Reserved
I2CIE.11: I2CSPIE
I2CIE.[15:12]: Reserved
TB0R (04h, 04h)
Initialization:
Read/Write Access:
TB0R.[15:0]:
______________________________________________________________________________________
I
This register is cleared to 0000h on all forms of reset.
Unrestricted read/write access.
I
condition is detected (I2CSRI = 1). Clearing this bit to 0 disables the START detection interrupt
from generating.
I
the transmit interrupt flag is set (I2CTXI = 1). Clearing this bit to 0 disables the transmit interrupt
from generating.
I
receive interrupt flag is set (I2CRXI = 1). Clearing this bit to 0 disables the receive interrupt from
generating.
I
clock stretch interrupt flag is set (I2CSTRI = 1). Clearing this bit disables the clock stretch interrupt
from generating.
I
condition is detected (I2CTOI = 1). Clearing this bit to 0 disables the timeout interrupt from
generating.
I
when the I
this bit to 0 disables the address match interrupt from generating.
I
master loses in an arbitration (I2CALI = 1). Clearing this bit to 0 disables the arbitration loss
interrupt from generating.
I
detected (I2CNACKI = 1). Clearing this bit to 0 disables the NACK detection interrupt from
generating.
I
to the CPU when general call is enabled (I2CGCEN = 1). Clearing this bit to 0 disables the general
call interrupt from generating.
I
receiver overrun condition is detected (I2CROI = 1). Clearing this bit to 0 disables the receiver
overrun detection interrupt from generating.
Reserved. Reads return 0.
I
condition is detected (I2CSPI = 1). Clearing this bit to 0 disables the STOP detection interrupt from
generating.
Reserved. Reads return 0.
Timer B 0 Capture/Reload Value
This register is cleared to 0000h on all forms of reset.
Unrestricted read/write.
Timer B Capture/Reload Bits 15:0. This register is used to capture the TB0V value when timer B is
configured in capture mode. This register is also used as the 16-bit reload value when timer B is
configured in autoreload mode.
2
2
2
2
2
2
2
2
2
2
2
2
C Interrupt Enable Register (16-Bit Register)
C START Interrupt Enable. Setting this bit to 1 causes an interrupt to the CPU when a START
C Transmit Complete Interrupt Enable. Setting this bit to 1 causes an interrupt to the CPU when
C Receive Ready Interrupt Enable. Setting this bit to 1 causes an interrupt to the CPU when the
C Clock Stretch Interrupt Enable. Setting this bit to 1 generates an interrupt to the CPU when the
C Timeout Interrupt Enable. Setting this bit to 1 causes an interrupt to the CPU when a timeout
C Slave Address Match Interrupt Enable. Setting this bit to 1 causes an interrupt to the CPU
C Arbitration Loss Enable. Setting this bit to 1 causes an interrupt to the CPU when the I
C NACK Interrupt Enable. Setting this bit to 1 causes an interrupt to the CPU when a NACK is
C General Call Interrupt Enable. Setting this bit to 1 generates an I2CGCI (general call interrupt)
C Receiver Overrun Interrupt Enable. Setting this bit to 1 causes an interrupt to the CPU when a
C STOP Interrupt Enable. Setting this bit to 1 causes an interrupt to the CPU when a STOP
Special Function Register Bit Descriptions (continued)
2
C controller detects an address that matches the I2CSLA value (I2CAMI = 1). Clearing
2
C