MAXQ3108-FFN+ Maxim Integrated Products, MAXQ3108-FFN+ Datasheet - Page 50

• Manufacturer Part Number: MAXQ3108-FFN+
• Description: IC MCU DUAL-CORE 16BIT 28-TSSOP
• Manufacturer: Maxim Integrated Products
• Series: MAXQ™r

Specifications of MAXQ3108-FFN+

• Core Processor: RISC
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 11K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-TSSOP
• Processor Series: MAXQ
• Core: RISC
• Data Bus Width: 16 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, JTAG, SPI
• Maximum Clock Frequency: 10 MHz
• Number Of Programmable I/os: 22
• Number Of Timers: 2
• Operating Supply Voltage: 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Low-Power, Dual-Core Microcontroller
This section contains detailed descriptions for each
peripheral device, however, many of the peripherals
are described in detail in the MAXQ Family User’s
Guide .
Table 5. Multipurpose Pin Description
50
I2CTO (0Eh, 04h)
Initialization:
Read/Write Access:
I2CTO.[7:0]:
I2CSLA (0Fh, 04h)
Initialization:
Read/Write Access:
I2CSLA.[9:0]:
I2CSLA.[15:10]: Reserved
PIN
1
2
3
4
______________________________________________________________________________________
PRIMARY
P2.0
P0.0
P0.1
P0.2
SECONDARY
MDIN1N
MDIN2P
RXD0
TXD0
I
This register is cleared to 00h on all forms of reset.
Unrestricted read/write access.
I
the number of I
timeout timer resets to 0 and starts to count after the I2CSTART bit is set or every time the SCL
goes low. When cleared to 00h, the timeout function is disabled and the I
high indefinitely during a transmission. When set to any other values, the I
timeout expires and sets the I2CTOI flag.
Note that these bits have no effect when the I
When operating in slave mode, SCL is controlled by an external master.
I
This register is cleared to 0000h on all forms of reset.
Unrestricted read/write access.
I
When a match to this address is detected, the I
transmitter with the I2CACK bit value if the I
set to 1 and the I2CMST bit is cleared to 0. An interrupt is generated to the CPU if enabled.
Reserved. Reads return 0.
2
2
2
2
C Timeout Register (8-Bit Register)
C Timeout Register Bits 7:0. This register is used only in master mode. This register determines
C Slave Address Register (16-Bit Register)
C Slave Address Register Bits 9:0. These address bits contain the address of the I
Special Function Register Bit Descriptions (continued)
TERTIARY
Peripherals
MOSI
INT0
INT1
T2P
2
C bit periods (SCL high + SCL low) the I
Do not enable both Manchester decoder 2 and SPI at the same time. If
neither is enabled, the GPIO port function is used.
Transmit data is only presented to the pin when a character is actually
being transmitted. To use this pin as full-time transmit data, set the GPIO
port pin to output and load a 1 in the output register. Do not enable an
interrupt on this pin if it is used for the serial transmit function.
Receive data function is only operational when the associated REN bit is
set is the SCON0 register. Do not enable an interrupt on this pin if it is
used for the serial receive function.
Do not enable outputs or clock gating on timer 2 when Manchester
decoder 1 is enabled. Also, do not enable INT2 when Manchester
decoder 1 is enabled or clock gating is used on timer 2.
I
2
C Timeout = I
Most of the peripheral devices on the MAXQ3108
require connections to other components. To minimize
the pin count, some peripherals share pins with other
peripherals. Obviously, only one peripheral can drive a
pin at any given time. Table 5 provides information on
how to use these multipurpose pins.
2
C Bit Rate x (I2CTO[7:0] + 1)
2
C module is enabled (I2CEN = 1). The I2CAMI flag is
2
C module is operating in slave mode (I2CMST = 0).
2
C controller automatically acknowledges the
2
C master will wait for SCL to go high. The
COMMENT
2
C waits for SCL to go
2
C waits until the
2
C device.
Pins