MC9S12XA256CAL Freescale Semiconductor, MC9S12XA256CAL Datasheet - Page 618

• Manufacturer Part Number: MC9S12XA256CAL
• Description: IC MCU 256K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XA256CAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 80MHz
• Connectivity: EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 91
• Eeprom Memory Size: 4KB
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• No. Of Timers: 1
• No. Of Pwm Channels: 8
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Processor Series: S12XA
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: EVB9S12XDP512E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 16 Channel)
• Package: 112LQFP
• Family Name: HCS12
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 2.5|5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 17 Memory Mapping Control (S12XMMCV2)
The MMCCTL0 register is used to control external bus functions, i.e., availability of chip selects.
618
CS[3:0]E
Field
3–0
Chip Select Enables — Each of these bits enables one of the external chip selects CS3, CS2, CS1, and CS0
outputs which are asserted during accesses to specific external addresses. The associated global address
ranges are shown in
Chip selects are only active if enabled in normal expanded mode, Emulation expanded mode and special test
mode. The function disabled in all other operating modes.
0 Chip select is disabled
1 Chip select is enabled
XGATE write access to this register during an CPU access which makes use
of this register could lead to unexpected results.
1
When the internal NVM is enabled (see ROMON in
Register
memory block.
(MMCCTL1)”) the CS0 is not asserted in the space occupied by this on-chip
Global Address Range
0x00_0800–0x0F_FFFF
0x10_0000–0x1F_FFFF
0x20_0000–0x3F_FFFF
0x40_0000–0x7F_FFFF
Table 1-6
Table 17-4. MMCCTL0 Field Descriptions
MC9S12XDP512 Data Sheet, Rev. 2.21
Table 17-5. Chip Select Signals
and
Table 1-21
CAUTION
and
Description
Figure
Section 1.3.2.5, “MMC Control
1-23.
Asserted Signal
CS0
CS3
CS2
CS1
1
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