ST72F324J6T6 STMicroelectronics, ST72F324J6T6 Datasheet - Page 65

• Manufacturer Part Number: ST72F324J6T6
• Description: IC MCU 8BIT 32K 44-TQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F324J6T6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Controller Family/series: ST7
• No. Of I/o's: 32
• Ram Memory Size: 1KB
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• No. Of Pwm Channels: 1
• Rohs Compliant: Yes
• Processor Series: ST72F3x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 1024 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4 bit
• Operating Supply Voltage: 3.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7F521-IND/USB, ST7232X-EVAL, ST7MDT20-DVP3, ST7MDT20J-EMU3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Cpu Family: ST7
• Device Core Size: 8b
• Frequency (max): 8MHz
• Total Internal Ram Size: 1KB
• # I/os (max): 32
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 3.8V
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: TQFP
• For Use With: 497-8222 - UPS (LINE INTERACTIVE - 450W)497-8436 - BOARD EVAL UPS 450W VOUT=220V497-6421 - BOARD EVAL DGTL BATT CHGR DESIGN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: In Transition
• Other names: 497-2108

16-BIT TIMER (Cont’d)
10.3.3.4 Output Compare
In this section, the index, i, may be 1 or 2 because
there are 2 output compare functions in the 16-bit
timer.
This function can be used to control an output
waveform or indicate when a period of time has
elapsed.
When a match is found between the Output Com-
pare register and the free running counter, the out-
put compare function:
Two 16-bit registers Output Compare Register 1
(OC1R) and Output Compare Register 2 (OC2R)
contain the value to be compared to the counter
register each timer clock cycle.
These registers are readable and writable and are
not affected by the timer hardware. A reset event
changes the OC
Timing resolution is one count of the free running
counter: (
Procedure:
To use the output compare function, select the fol-
lowing in the CR2 register:
– Set the OCiE bit if an output is needed then the
– Select the timer clock (CC[1:0]) (see
And select the following in the CR1 register:
– Select the OLVLi bit to applied to the OCMPi pins
– Set the OCIE bit to generate an interrupt if it is
When a match is found between OCRi register
and CR register:
– OCFi bit is set.
OCMPi pin is dedicated to the output compare i
signal.
Clock Control
after the match occurs.
needed.
– Assigns pins with a programmable value if the
– Sets a flag in the status register
– Generates an interrupt if enabled
OCiR
OCiE bit is set
f
CPU/
CC[1:0]
Bits).
i
R value to 8000h.
MS Byte
OCiHR
).
LS Byte
OCiLR
Table 16
– The OCMPi pin takes OLVLi bit value (OCMPi
– A timer interrupt is generated if the OCIE bit is
The OC
ing application can be calculated using the follow-
ing formula:
Where:
∆
f
PRESC
If the timer clock is an external clock, the formula
is:
Where:
∆
f
Clearing the output compare interrupt request (i.e.
clearing the OCFi bit) is done by:
1. Reading the SR register while the OCFi bit is
2. An access (read or write) to the OCiLR register.
The following procedure is recommended to pre-
vent the OCFi bit from being set between the time
it is read and the write to the OC
– Write to the OCiHR register (further compares
– Read the SR register (first step of the clearance
– Write to the OCiLR register (enables the output
CPU
EXT
t
t
pin latch is forced low during reset).
set in the CR1 register and the I bit is cleared in
the CC register (CC).
are inhibited).
of the OCFi bit, which may be already set).
compare function and clears the OCFi bit).
set.
i
R register value required for a specific tim-
= Output compare period (in seconds)
= CPU clock frequency (in hertz)
= Timer prescaler factor (2, 4 or 8 de-
= Output compare period (in seconds)
= External timer clock frequency (in hertz)
pending on CC[1:0] bits, see
Clock Control
∆
∆
OCiR =
OCiR =
ST72324Jx ST72324Kx
∆t
Bits)
∆t
*
PRESC
f
EXT
*
f
CPU
i
R register:
Table 16
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