ST72F324J6T6 STMicroelectronics, ST72F324J6T6 Datasheet - Page 34

• Manufacturer Part Number: ST72F324J6T6
• Description: IC MCU 8BIT 32K 44-TQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F324J6T6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Controller Family/series: ST7
• No. Of I/o's: 32
• Ram Memory Size: 1KB
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• No. Of Pwm Channels: 1
• Rohs Compliant: Yes
• Processor Series: ST72F3x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 1024 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4 bit
• Operating Supply Voltage: 3.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7F521-IND/USB, ST7232X-EVAL, ST7MDT20-DVP3, ST7MDT20J-EMU3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Cpu Family: ST7
• Device Core Size: 8b
• Frequency (max): 8MHz
• Total Internal Ram Size: 1KB
• # I/os (max): 32
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 3.8V
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: TQFP
• For Use With: 497-8222 - UPS (LINE INTERACTIVE - 450W)497-8436 - BOARD EVAL UPS 450W VOUT=220V497-6421 - BOARD EVAL DGTL BATT CHGR DESIGN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: In Transition
• Other names: 497-2108

ST72324Jx ST72324Kx
INTERRUPTS (Cont’d)
7.5 INTERRUPT REGISTER DESCRIPTION
CPU CC REGISTER INTERRUPT BITS
Read/Write
Reset Value: 111x 1010 (xAh)
Bit 5, 3 = I1, I0 Software Interrupt Priority
These two bits indicate the current interrupt soft-
ware priority.
These two bits are set/cleared by hardware when
entering in interrupt. The loaded value is given by
the corresponding bits in the interrupt software pri-
ority registers (ISPRx).
They can be also set/cleared by software with the
RIM, SIM, HALT, WFI, IRET and PUSH/POP in-
structions (see “Interrupt Dedicated Instruction
Set” table).
*Note: TRAP and RESET events can interrupt a
level 3 program.
34/164
1
Level 0 (main)
Level 1
Level 2
Level 3 (= interrupt disable*)
Interrupt Software Priority
7
1
1
I1
H
I0
Level
High
Low
N
I1
1
0
0
1
Z
I0
0
1
0
1
C
0
INTERRUPT SOFTWARE PRIORITY REGIS-
TERS (ISPRX)
Read/Write (bit 7:4 of ISPR3 are read only)
Reset Value: 1111 1111 (FFh)
These four registers contain the interrupt software
priority of each interrupt vector.
– Each interrupt vector (except RESET and TRAP)
– Each I1_x and I0_x bit value in the ISPRx regis-
– Level 0 can not be written (I1_x=1, I0_x=0). In
The RESET, and TRAP vectors have no software
priorities. When one is serviced, the I1 and I0 bits
of the CC register are both set.
Caution: If the I1_x and I0_x bits are modified
while the interrupt x is executed the following be-
haviour has to be considered: If the interrupt x is
still pending (new interrupt or flag not cleared) and
the new software priority is higher than the previ-
ous one, the interrupt x is re-entered. Otherwise,
the software priority stays unchanged up to the
next interrupt request (after the IRET of the inter-
rupt x).
has corresponding bits in these registers where
its own software priority is stored. This corre-
spondance is shown in the following table.
ters has the same meaning as the I1 and I0 bits
in the CC register.
this case, the previously stored value is kept. (ex-
ample: previous=CFh, write=64h, result=44h)
ISPR0
ISPR1
ISPR2
ISPR3
Vector address
FFFBh-FFFAh
FFE1h-FFE0h
FFF9h-FFF8h
I1_11 I0_11 I1_10 I0_10 I1_9
I1_3
I1_7
7
1
...
I0_3
I0_7
1
I1_2
I1_6
1
I0_2
I0_6
1
I1_13 and I0_13 bits
I1_0 and I0_0 bits*
I1_1 and I0_1 bits
I1_13 I0_13 I1_12 I0_12
I1_1
I1_5
ISPRx bits
I0_1
I0_5
I0_9
...
I1_0
I1_4
I1_8
I0_0
I0_4
I0_8
0