EP9312-CBZ Cirrus Logic Inc, EP9312-CBZ Datasheet - Page 727

• Manufacturer Part Number: EP9312-CBZ
• Description: IC ARM9 SOC UNIVERSAL 352PBGA
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9312-CBZ

• Core Size: 16/32-Bit
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 352-BGA
• Controller Family/series: (ARM9)
• No. Of I/o's: 16
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 4
• No. Of Pwm Channels: 2
• Digital Ic Case Style: BGA
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1258

DS785UM1
Default:
Definition:
Bit Descriptions:
0x0000_0000
SSPCR1 is the control register 1 and contains six different bit fields, which
control various functions within the SSP.
RSVD:
SOD:
MS:
SSE:
LBM:
RORIE:
TIE:
Copyright 2007 Cirrus Logic
Reserved. Unknown During Read.
Slave-mode output disable. This bit is relevant only in the
slave mode (MS=1). In multiple-slave systems, it is
possible for an SSPMS master to broadcast a message to
all slaves in the system while ensuring that only one slave
drives data onto its serial output line. In such systems the
RXD lines from multiple slaves can be tied together. To
operate in such systems, the SOD may be set if the SSP
slave is not supposed to drive the SSPTXD line.
0 - SSP may drive the SSPTXD output in slave mode.
1 - SSP must not drive the SSPTXD output in slave
modes.
Master / Slave mode select. This bit can be modified only
when the SSP is disabled (SSE=0).
0 - Device configured as master (default).
1 - Device configured as slave.
Synchronous serial port enable:
0 - SSP operation disabled
1 - SSP operation enabled.
Loop back mode:
0 - Normal serial port operation enabled.
1 - Output of transmit serial shifter is connected to input of
receive serial shifter internally.
Receive FIFO overrun interrupt enable:
0 - Overrun detection is disabled. Overrun condition does
not generate the SSPRORINTR interrupt.
1 - Overrun detection is enabled. Overrun condition
generates the SSPRORINTR interrupt.
Transmit FIFO interrupt enable:
0 - Transmit FIFO half-full or less condition does not
generate the SSPTXINTR interrupt.
1 - Transmit FIFO half-full or less condition generates the
SSPTXINTR interrupt.
Synchronous Serial Port
EP93xx User’s Guide
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