EP9312-CBZ Cirrus Logic Inc, EP9312-CBZ Datasheet - Page 388

• Manufacturer Part Number: EP9312-CBZ
• Description: IC ARM9 SOC UNIVERSAL 352PBGA
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9312-CBZ

• Core Size: 16/32-Bit
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 352-BGA
• Controller Family/series: (ARM9)
• No. Of I/o's: 16
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 4
• No. Of Pwm Channels: 2
• Digital Ic Case Style: BGA
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1258

9
TXBufThrshld
9-86
1/10/100 Mbps Ethernet LAN Controller
EP93xx User’s Guide
31
15
Address:
Suggested Value:
Chip Reset:
Soft Reset:
Definition:
Bit Descriptions:
30
14
29
13
RSVD
RSVD
28
12
RDST:
0x8001_00D4 - Read/Write
0020_0010
0x0000_0000
Unchanged
Transmit Buffer Threshold register. The transmit buffer thresholds are used to
set a limit on the amount of empty space allowed in the transmit FIFO before a
bus request will be scheduled. When the number of empty words in the FIFO
exceeds the threshold value, the Descriptor Processor will schedule a bus
request to transfer data. The actual posting of the bus request may be delayed
due to lack of resources in the MAC, such as no active transmit descriptor.
The lower two bits of the thresholds are always zero.
RSVD:
TDHT:
27
11
26
10
Copyright 2007 Cirrus Logic
25
9
Receive Data Soft Threshold. The hard and soft threshold
work in exactly the same manner except one. The soft
threshold will not cause a bus request to be made if the
bus is currently in use, but only when it is deemed to be
idle (no transfers for four AHB clocks). The hard threshold
takes effect immediately, regardless of the state of the bus.
This operation allows for more efficient use of the AHB bus
by allowing smaller transfers to take place when the bus is
lightly loaded and requesting larger transfers only when
the bus is more heavily loaded.
Reserved. Unknown During Read.
Transmit Data Hard Threshold.
24
8
23
7
22
6
TDHT
TDST
21
5
20
4
19
3
18
2
17
0
1
0
DS785UM1
16
0
0
0