EP9312-CBZ Cirrus Logic Inc, EP9312-CBZ Datasheet - Page 201

• Manufacturer Part Number: EP9312-CBZ
• Description: IC ARM9 SOC UNIVERSAL 352PBGA
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9312-CBZ

• Core Size: 16/32-Bit
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 352-BGA
• Controller Family/series: (ARM9)
• No. Of I/o's: 16
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 4
• No. Of Pwm Channels: 2
• Digital Ic Case Style: BGA
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1258

DS785UM1
D18
Fra
me
Ctr
X
X
At clock 0, the HCNT, VCNT and FRAME counters are 0x0. The pixel to display is a 5, which
translates to register base + 0x94, bit D0. At the next clock tick, the fastest running counter
(HCNT) has incremented, but VCNT and FRAME remain the same. Given the same pixel
value (5), bit position D1 is used as the value that is sent to the display.
Ve
17
Ct
rt
D
X
X
r
Ctr
Ho
D1
rz
6
X
X
Clock
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
address
register
(pixels)
(lines)
VCNT
HCNT
base +
base +
base +
base +
base +
base +
base +
base +
0x1C
0x3C
0x5C
0x7C
0x00
0x20
0x40
0x60
HCNT
3
0
1
2
3
0
1
2
3
0
1
2
3
“
“
“
15
11
11
D
0
0
0
0
1
1
1
1
Table 7-5. Grayscale Timing Diagram (Continued)
VCNT
11
10
14
D
0
0
0
0
1
1
1
1
Copyright 2007 Cirrus Logic
3
0
0
0
0
0
0
0
0
0
0
0
0
“
“
“
01
13
11
D
0
0
0
0
1
1
1
1
Table 7-6. Programming Format
Raster Engine With Analog/LCD Integrated Timing and Interface
11
00
12
D
0
0
0
0
1
1
1
1
FRAME
0
1
1
1
1
2
2
2
2
3
3
3
3
“
“
“
10
11
11
D
0
0
0
0
1
1
1
1
D1
10
10
0
0
0
0
0
1
1
1
1
PIXEL
D
1
0
0
1
9
0
0
0
0
1
1
1
1
5
5
5
5
5
5
5
5
5
5
5
5
5
“
“
“
1
0
0
0
D
8
0
0
0
0
1
1
1
1
0
1
1
1
D
7
0
0
0
0
1
1
1
1
D
0
1
1
0
6
0
0
0
0
1
1
1
1
Register Address / Value
D
0
1
0
1
5
0
0
0
0
1
1
1
1
(base + 94) / D15
(base + b4) / D0
(base + b4) / D1
(base + b4) / D2
(base + b4) / D3
(base + d4) / D0
(base + d4) / D1
(base + d4) / D2
(base + d4) / D3
(base + f4) / D0
(base + f4) / D1
(base + f4) / D2
(base + f4) / D3
0
1
0
0
D
4
0
0
0
0
1
1
1
1
0
0
1
1
D
3
0
0
0
0
1
1
1
1
0
0
1
0
D
2
0
0
0
0
1
1
1
1
EP93xx User’s Guide
D
0
0
0
1
1
0
0
0
0
1
1
1
1
D
0
0
0
0
0
0
0
0
0
1
1
1
1
GrySclLU
Address
Frame
*4
00
01
10
11
00
01
10
11
T
7-19
Pix
000
000
000
000
Val
111
111
111
111
ue
el
7