ATMEGA644P-A15MZ Atmel, ATMEGA644P-A15MZ Datasheet - Page 238

• Manufacturer Part Number: ATMEGA644P-A15MZ
• Description: MCU AVR 64KB FLASH 16MHZ 44QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA644P-A15MZ

• Package / Case: 44-VQFN Exposed Pad
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Number Of I /o: 32
• Eeprom Size: 2K x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Program Memory Size: 64KB (64K x 8)
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Connectivity: I²C, SPI, UART/USART
• Core Size: 8-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

19.9.4
19.9.5
19.9.6
238
ATmega164P/324P/644P
TWDR – TWI Data Register
TWAR – TWI (Slave) Address Register
TWAMR – TWI (Slave) Address Mask Register
In Transmit mode, TWDR contains the next byte to be transmitted. In Receive mode, the TWDR
contains the last byte received. It is writable while the TWI is not in the process of shifting a byte.
This occurs when the TWI Interrupt Flag (TWINT) is set by hardware. Note that the Data Regis-
ter cannot be initialized by the user before the first interrupt occurs. The data in TWDR remains
stable as long as TWINT is set. While data is shifted out, data on the bus is simultaneously
shifted in. TWDR always contains the last byte present on the bus, except after a wake up from
a sleep mode by the TWI interrupt. In this case, the contents of TWDR is undefined. In the case
of a lost bus arbitration, no data is lost in the transition from Master to Slave. Handling of the
ACK bit is controlled automatically by the TWI logic, the CPU cannot access the ACK bit directly.
• Bits 7:0 – TWD: TWI Data Register
These eight bits constitute the next data byte to be transmitted, or the latest data byte received
on the 2-wire Serial Bus.
The TWAR should be loaded with the 7-bit Slave address (in the seven most significant bits of
TWAR) to which the TWI will respond when programmed as a Slave Transmitter or Receiver,
and not needed in the Master modes. In multimaster systems, TWAR must be set in masters
which can be addressed as Slaves by other Masters.
The LSB of TWAR is used to enable recognition of the general call address (0x00). There is an
associated address comparator that looks for the slave address (or general call address if
enabled) in the received serial address. If a match is found, an interrupt request is generated.
• Bits 7:1 – TWA: TWI (Slave) Address Register
These seven bits constitute the slave address of the TWI unit.
• Bit 0 – TWGCE: TWI General Call Recognition Enable Bit
If set, this bit enables the recognition of a General Call given over the 2-wire Serial Bus.
• Bits 7:1 – TWAM: TWI Address Mask
Bit
(0xBB)
Read/Write
Initial Value
Bit
(0xBA)
Read/Write
Initial Value
Bit
(0xBD)
Read/Write
Initial Value
TWD7
TWA6
R/W
R/W
R/W
7
1
7
1
7
0
TWD6
TWA5
R/W
R/W
R/W
6
1
6
1
6
0
TWD5
TWA4
R/W
R/W
R/W
5
1
5
1
5
0
TWAM[6:0]
TWD4
TWA3
R/W
R/W
R/W
4
1
4
1
4
0
TWD3
TWA2
R/W
R/W
R/W
3
1
3
1
3
0
TWD2
TWA1
R/W
R/W
R/W
2
1
2
1
2
0
TWD1
TWA0
R/W
R/W
R/W
1
1
1
1
1
0
TWGCE
TWD0
R/W
R/W
R
0
1
0
0
0
–
0
7674F–AVR–09/09
TWAMR
TWDR
TWAR