PIC18F452-E/PT Microchip Technology, PIC18F452-E/PT Datasheet - Page 61

• Manufacturer Part Number: PIC18F452-E/PT
• Description: IC MCU CMOS 40MHZ 16K FLSH44TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F452-E/PT

• Core Size: 8-Bit
• Program Memory Size: 32KB (16K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 44-TQFP, 44-VQFP
• Controller Family/series: PIC18
• No. Of I/o's: 34
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 1.5KB
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Package: 44TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 34
• Interface Type: I2C/SPI/USART
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5.3
The TBLRD instruction is used to retrieve data from pro-
gram memory and place into data RAM. Table Reads
from program memory are performed one byte at a
time.
FIGURE 5-4:
EXAMPLE 5-1:
© 2006 Microchip Technology Inc.
READ_WORD
Reading the FLASH Program
Memory
Instruction Register
MOVLW CODE_ADDR_UPPER
MOVWF TBLPTRU
MOVLW CODE_ADDR_HIGH
MOVWF TBLPTRH
MOVLW CODE_ADDR_LOW
MOVWF TBLPTRL
TBLRD*+
MOVF TABLAT, W
MOVWF WORD_EVEN
TBLRD*+
MOVF TABLAT, W
MOVWF WORD_ODD
(IR)
READS FROM FLASH PROGRAM MEMORY
READING A FLASH PROGRAM MEMORY WORD
(Even Byte Address)
FETCH
Program Memory
; Load TBLPTR with the base
; address of the word
; read into TABLAT and increment
; get data
; read into TABLAT and increment
; get data
(Odd Byte Address)
TBLPTR points to a byte address in program space.
Executing TBLRD places the byte pointed to into
TABLAT. In addition, TBLPTR can be modified
automatically for the next Table Read operation.
The internal program memory is typically organized by
words. The Least Significant bit of the address selects
between the high and low bytes of the word. Figure 5-4
shows the interface between the internal program
memory and the TABLAT.
TBLPTR = xxxxx1
TBLRD
Read Register
PIC18FXX2
TABLAT
TBLPTR = xxxxx0
DS39564C-page 59