PIC18F452-E/P Microchip Technology, PIC18F452-E/P Datasheet - Page 15

• Manufacturer Part Number: PIC18F452-E/P
• Description: IC MCU CMOS 40MHZ 16K FLSH 40DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F452-E/P

• Program Memory Type: FLASH
• Program Memory Size: 32KB (16K x 16)
• Package / Case: 40-DIP (0.600", 15.24mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 34
• Eeprom Size: 256 x 8
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1.5 KB
• Interface Type: MSSP/SPI/I2C/PSP/USART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 34
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM163022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Package: 40PDIP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: ACICE0206 - ADAPTER MPLABICE 40P 600 MIL
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

TABLE 3-5:
 2010 Microchip Technology Inc.
Step 1: Direct access to config memory.
Step 2: Configure device for single panel writes.
Step 3: Direct access to code memory.
Step 4: Set the Table Pointer for the block to be erased.
Step 5: Enable memory writes and setup an erase.
Step 6: Perform required sequence.
Step 7: Initiate erase.
Step 8: Wait for P11+P10 and then disable writes.
Step 9: Load write buffer for panel. The correct panel will be selected based on the Table Pointer.
To continue writing data, repeat step 8, where the Address Pointer is incremented by 8 at each iteration of the loop.
Command
0000
0000
0000
0000
0000
0000
0000
0000
1100
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
1101
1101
1101
1111
0000
4-Bit
8E A6
8C A6
0E 3C
6E F8
0E 00
6E F7
0E 06
6E F6
00 00
8E A6
9C A6
0E <Addr[21:16]>
6E F8
0E <Addr[8:15]>
6E F7
0E <Addr[7:0]>
6E F6
84 A6
88 A6
0E 55
6E A7
0E AA
6E A7
82 A6
00 00
94 A6
0E <Addr[8:15]>
6E F7
0E <Addr[7:0]>
6E F6
<LSB><MSB>
<LSB><MSB>
<LSB><MSB>
<LSB><MSB>
00 00
MODIFYING CODE MEMORY
Data Payload
BSF
BSF
MOVLW 3Ch
MOVWF TBLPTRU
MOVLW 00h
MOVWF TBLPTRH
MOVLW 06h
MOVWF TBLPTRL
Write 00h to 3C0006h to enable single-panel writes.
BSF EECON1, EEPGD
BCF EECON1, CFGS
MOVLW <Addr[21:16]>
MOVWF TBLPTRU
MOVLW <Addr[8:15]>
MOVWF TBLPTRH
MOVLW <Addr[7:0]>
MOVWF TBLPTRL
BSF EECON1, WREN
BSF EECON1, FREE
MOVLW 55h
MOVWF EECON2
MOVLW 0AAh
MOVWF EECON2
BSF EECON1, WR
NOP
BCF EECON1, WREN
MOVLW <Addr[8:15]>
MOVWF TBLPTRH
MOVLW <Addr[7:0]>
MOVWF TBLPTRL
Write 2 bytes and post-increment address by 2
Write 2 bytes and post-increment address by 2
Write 2 bytes and post-increment address by 2
Write 2 bytes and start programming
NOP - hold SCLK high for time P9
EECON1, EEPGD
EECON1, CFGS
Core Instruction
PIC18FXX2/XX8
DS39576C-page 15