PIC16LC72A-04I/SO Microchip Technology, PIC16LC72A-04I/SO Datasheet - Page 62

• Manufacturer Part Number: PIC16LC72A-04I/SO
• Description: IC MCU OTP 2KX14 A/D PWM 28SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16LC72A-04I/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: OTP
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 5x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

PIC16C62B/72A
10.10
The interrupt control register (INTCON) records individ-
ual interrupt requests in flag bits. It also has individual
and global interrupt enable bits.
A global interrupt enable bit, GIE (INTCON<7>)
enables or disables all interrupts. When bit GIE is
enabled, and an interrupt’s flag bit and mask bit are set,
the interrupt will vector immediately. Individual inter-
rupts can be disabled through their corresponding
enable bits in various registers. Individual interrupt flag
bits are set regardless of the status of the GIE bit. The
GIE bit is cleared on reset.
The “return from interrupt” instruction, RETFIE, exits
the interrupt routine and sets the GIE bit, which re-
enables interrupts.
The RB0/INT pin interrupt, the RB port change interrupt
and the TMR0 overflow interrupt flags are contained in
the INTCON register.
FIGURE 10-7: INTERRUPT LOGIC
DS35008B-page 62
Note:
TMR1IF
TMR1IE
Interrupts
Note 1: The A/D module is not implemented on the PIC16C62B.
Individual interrupt flag bits are set regard-
less of the status of their corresponding
mask bit or the GIE bit.
TMR2IF
TMR2IE
ADIF
ADIE
SSPIF
SSPIE
CCP1IF
CCP1IE
(1)
(1)
Preliminary
T0IF
T0IE
INTF
INTE
RBIF
RBIE
PEIE
GIE
The peripheral interrupt flags are contained in the spe-
cial function registers PIR1 and PIR2. The correspond-
ing interrupt enable bits are contained in special
function registers PIE1 and PIE2, and the peripheral
interrupt enable bit is contained in special function reg-
ister INTCON.
When an interrupt is responded to, the GIE bit is
cleared to disable any further interrupts, the return
address is pushed onto the stack and the PC is loaded
with 0004h. Once in the interrupt service routine, the
source of the interrupt can be determined by polling the
interrupt flag bits. The interrupt flag bit must be cleared
in software before re-enabling interrupts to avoid recur-
sive interrupts.
For external interrupt events, such as the INT pin or
PORTB change interrupt, the interrupt latency will be
three or four instruction cycles, depending on when the
interrupt event occurs. The latency is the same for one
or two cycle instructions. Individual interrupt flag bits
are set regardless of the status of their corresponding
mask bit or the GIE bit
Wake-up (If in SLEEP mode)
1999 Microchip Technology Inc.
Interrupt to CPU