ATA6613P-PLQW Atmel, ATA6613P-PLQW Datasheet - Page 279
ATA6613P-PLQW
Manufacturer Part Number
ATA6613P-PLQW
Description
MCU W/LIN TXRX REG WTCHDG 48-QFN
Manufacturer
Atmel
Series
AVR® ATA66 LIN-SBCr
Datasheet
1.ATA6612-EK.pdf
(364 pages)
Specifications of ATA6613P-PLQW
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-QFN Exposed Pad
Processor Series
ATA6x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
23
Number Of Timers
3
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATA6613P-PLQW
Manufacturer:
ATMEL
Quantity:
5 000
Part Number:
ATA6613P-PLQW
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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9111H–AUTO–01/11
Table 6-100. ADC Prescaler Selections
• Bit 4 – ADIF: ADC Interrupt Flag
• Bit 3 – ADIE: ADC Interrupt Enable
• Bits 2:0 – ADPS2:0: ADC Prescaler Select Bits
This bit is set when an ADC conversion completes and the Data Registers are updated.
The ADC Conversion Complete Interrupt is executed if the ADIE bit and the I-bit in SREG
are set. ADIF is cleared by hardware when executing the corresponding interrupt handling
vector. Alternatively, ADIF is cleared by writing a logical one to the flag. Beware that if
doing a Read-Modify-Write on ADCSRA, a pending interrupt can be disabled. This also
applies if the SBI and CBI instructions are used.
When this bit is written to one and the I-bit in SREG is set, the ADC Conversion Complete
Interrupt is activated.
These bits determine the division factor between the system clock frequency and the input
clock to the ADC.
ADPS2
0
0
0
0
1
1
1
1
ADPS1
0
0
1
1
0
0
1
1
ADPS0
Atmel ATA6612/ATA6613
0
1
0
1
0
1
0
1
Division Factor
128
16
32
64
2
2
4
8
279
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