ATA6613P-PLQW Atmel, ATA6613P-PLQW Datasheet - Page 175

• Manufacturer Part Number: ATA6613P-PLQW
• Description: MCU W/LIN TXRX REG WTCHDG 48-QFN
• Manufacturer: Atmel
• Series: AVR® ATA66 LIN-SBCr

Specifications of ATA6613P-PLQW

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-QFN Exposed Pad
• Processor Series: ATA6x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 3
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9111H–AUTO–01/11
Table 6-60
correct PWM mode.
Table 6-60.
Note:
Table 6-61.
Table 6-62
mode.
Table 6-62.
Note:
• Bits 5:4 – COM2B1:0: Compare Match Output B Mode
COM2A1
COM2B1
COM2B1
These bits control the Output Compare pin (OC2B) behavior. If one or both of the
COM2B1:0 bits are set, the OC2B output overrides the normal port functionality of the I/O
pin it is connected to. However, note that the Data Direction Register (DDR) bit corre-
sponding to the OC2B pin must be set in order to enable the output driver.
When OC2B is connected to the pin, the function of the COM2B1:0 bits depends on the
WGM22:0 bit setting.
WGM22:0 bits are set to a normal or CTC mode (non-PWM).
0
0
1
1
0
0
1
1
0
0
1
1
1. A special case occurs when OCR2A equals TOP and COM2A1 is set. In this case, the Com-
1. A special case occurs when OCR2B equals TOP and COM2B1 is set. In this case, the Com-
pare Match is ignored, but the set or clear is done at TOP. See
on page 171
shows the COM2B1:0 bit functionality when the WGM22:0 bits are set to fast PWM
pare Match is ignored, but the set or clear is done at TOP. See
on page 171
shows the COM2A1:0 bit functionality when the WGM22:0 bits are set to phase
Compare Output Mode, Phase Correct PWM Mode
Compare Output Mode, non-PWM Mode
Compare Output Mode, Fast PWM Mode
COM2A0
COM2B0
COM2B0
0
1
0
1
0
1
0
1
0
1
0
1
for more details.
for more details.
Table 6-61
Description
Normal port operation, OC2A disconnected.
WGM22 = 0: Normal Port Operation, OC2A Disconnected.
WGM22 = 1: Toggle OC2A on Compare Match.
Clear OC2A on Compare Match when up-counting. Set OC2A on
Compare Match when down-counting.
Set OC2A on Compare Match when up-counting. Clear OC2A on
Compare Match when down-counting.
Description
Normal port operation, OC2B disconnected.
Toggle OC2B on Compare Match
Clear OC2B on Compare Match
Set OC2B on Compare Match
Description
Normal port operation, OC2B disconnected.
Reserved
Clear OC2B on Compare Match, set OC2B at TOP
Set OC2B on Compare Match, clear OC2B at TOP
shows the COM2B1:0 bit functionality when the
Atmel ATA6612/ATA6613
(1)
(1)
“Phase Correct PWM Mode”
“Phase Correct PWM Mode”
175