M30879FLGP#U3 Renesas Electronics America, M30879FLGP#U3 Datasheet - Page 412
M30879FLGP#U3
Manufacturer Part Number
M30879FLGP#U3
Description
IC M32C/87 MCU FLASH 100LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Specifications of M30879FLGP#U3
Core Size
16/32-Bit
Program Memory Size
1MB (1M x 8)
Core Processor
M32C/80
Speed
32MHz
Connectivity
CAN, EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
85
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Controller Family/series
M32C
No. Of I/o's
85
Ram Memory Size
48KB
Cpu Speed
32MHz
No. Of Timers
2
Digital Ic Case Style
LQFP
Embedded Interface Type
CAN, I2C, UART
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M30879FLGP#U3M30879FLGP#U5
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 22. Intelligent I/O (Group 0 and 1 Communication Function)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 388 of 587
Figure 22.53
Figure 22.54
The above applies under the following conditions:
- The STPS bit in the G1MR register is set to 0 (1 stop bit)
- The PRYE bit in the G1MR register is set to 0 (parity disabled)
- The UFORM bit in the G1MR register is set to 0 (LSB first)
- The INV bit in registers G1POCR0 to G1POCR7 is set to 0 (output not inverted)
The SIO1RR bit
Internal receive
Internal receive
The above applies under the following conditions:
- The STPS bit in the G1MR register is set to 0 (1 stop bit)
- The PRYE bit in the G1MR register is set to 0 (parity disabled)
- The UFORM bit in the G1MR register is set to 0 (LSB first)
- The INV bit in registers G1POCR0 to G1POCR7 is set to 0 (output not inverted)
- The IRS bit in the G1MR register is set to 0 (no data in the G1TB register)
Internal transmit
clock
ISTXD1 pin
TI bit in the G1CR
register
TXEPT bit in the
G1CR register
SIO1TR bit in the
IIO3IR register
Base timer 1
ISRXD1 pin
ISRXD1 pin
The RI bit
clock
clock
Transmit Operation in Group 1 UART Mode
Receive Operation in Group 1 UART Mode
0000h
n + 1
"H"
"L"
1
0
1
0
"H"
"L"
1
0
1
0
1
0
Synchronization
ST
ST
Set data in the G1TB register
D0 D1 D2 D3 D4 D5 D6 D7
D0
Start Bit (ST)
D1
2 (n + 2)
D2
fBT1
Set to 0 by a program
D3
Cycle
D4
D5
SP
D6
D7
SIO1RR bit: The bit in the IIO2IR register
RI bit: The bit in the G1CR register
SP
ST
Set data in the G1TB register
D0 D1 D2 D3 D4 D5 D6 D7
D0
Set to 0 by a program
Read the G1RB register
ST
D0
D1
D2
SP
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