M30879FLGP#U3 Renesas Electronics America, M30879FLGP#U3 Datasheet - Page 137
M30879FLGP#U3
Manufacturer Part Number
M30879FLGP#U3
Description
IC M32C/87 MCU FLASH 100LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Specifications of M30879FLGP#U3
Core Size
16/32-Bit
Program Memory Size
1MB (1M x 8)
Core Processor
M32C/80
Speed
32MHz
Connectivity
CAN, EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
85
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Controller Family/series
M32C
No. Of I/o's
85
Ram Memory Size
48KB
Cpu Speed
32MHz
No. Of Timers
2
Digital Ic Case Style
LQFP
Embedded Interface Type
CAN, I2C, UART
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M30879FLGP#U3M30879FLGP#U5
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 113 of 587
11.6
11.6.1
Table 11.4
11.6.2
Software interrupts occur when their corresponding instructions are executed. The INTO instruction, however,
requires the O flag in the FLG register to be 1. Special interrupts occur when their corresponding interrupt requests
are generated.
For the peripheral function interrupts to be acknowledged, the following conditions must be met:
The I flag, IPL, IR bit, and bits ILVL2 to ILVL0 are independent of each other. The I flag and IPL are in the FLG
register. The IR bit and bits ILVL2 to ILVL0 are in the Interrupt Control Register.
IPL2 to IPL0
•
•
•
The I flag enables and disables maskable interrupts. When the I flag is set to 1 (enable), all maskable interrupts
are enabled; when the I flag is set to 0 (disable), they are disabled. The I flag automatically becomes 0 after
reset.
IPL is 3 bits wide and indicates the Interrupt Priority Level (IPL) from level 0 to level 7. If a requested interrupt
has higher priority level than IPL, the interrupt is acknowledged.
Table 11.4 lists interrupt priority levels associated with IPL.
The Interrupt Control Registers are used to control the peripheral function interrupts. Figures 11.4 and 11.5
show the Interrupt Control Registers. Figure 11.6 shows the RLVL register.
I flag = 1
IR bit = 1
Bits ILVL2 to ILVL0 > IPL
Interrupt Request Acknowledgement
0
1
2
3
4
5
6
7
I Flag and IPL
Interrupt Control Registers and RLVL Register
Interrupt Priority Levels
Level 1 and above
Level 2 and above
Level 3 and above
Level 4 and above
Level 5 and above
Level 6 and above
Level 7 and above
All maskable interrupts are disabled
Required Interrupt Priority Levels to Be Acknowledged
for Maskable Interrupts
11. Interrupts
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