M37544G2AGP#U0 Renesas Electronics America, M37544G2AGP#U0 Datasheet - Page 65

• Manufacturer Part Number: M37544G2AGP#U0
• Description: IC 740 MCU OTP 8K 32LQFP
• Manufacturer: Renesas Electronics America
• Series: 740/38000r

Specifications of M37544G2AGP#U0

• Core Processor: 740
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SIO, UART/USART
• Peripherals: WDT
• Number Of I /o: 25
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: QzROM
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 6x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Rev.1.04
REJ03B0012-0104Z
7544 Group
Notes on Serial I/O
1. Clock synchronous serial I/O
(1) When the transmit operation is stopped, clear the serial I/O en-
<Reason>
Since transmission is not stopped and the transmission circuit is
not initialized even if only the serial I/O enable bit is cleared to “0”
(serial I/O disabled), the internal transmission is running (in this
case, since pins TxD, RxD, S
the transmission data is not output). When data is written to the
transmit buffer register in this state, data starts to be shifted to the
transmit shift register. When the serial I/O enable bit is set to “1” at
this time, the data during internally shifting is output to the TxD pin
and an operation failure occurs.
(2) When the receive operation is stopped, clear the receive en-
(3) When the transmit/receive operation is stopped, clear both the
<Reason>
In the clock synchronous serial I/O mode, the same clock is used
for transmission and reception.
If any one of transmission and reception is disabled, a bit error oc-
curs because transmission and reception cannot be synchronized.
In this mode, the clock circuit of the transmission circuit also oper-
ates for data reception. Accordingly, the transmission circuit does
not stop by clearing only the transmit enable bit to “0” (transmit
disabled). Also, the transmission circuit cannot be initialized even
if the serial I/O enable bit is cleared to “0” (serial I/O disabled)
(same as (1)).
(4) When signals are output from the S
(5) When the S
2. UART
When the transmit operation is stopped, clear the transmit enable
bit to “0” (transmit disabled).
<Reason>
Same as (1) shown on the above “1. Clock synchronous serial I/
O“.
When the receive operation is stopped, clear the receive enable
bit to “0” (receive disabled).
When the transmit/receive operation is stopped, clear the transmit
enable bit to “0” (transmit disabled) and receive enable bit to “0”
(receive disabled).
able bit (bit 7) and the transmit enable bit (bit 4 of serial I/O
control register (address 1A
disabled).
able bit (bit 5) to “0” (receive disabled), or clear the serial I/O
enable bit (bit 7 of serial I/O control register (address 1A
“0” (serial I/O disabled).
transmit enable bit and receive enable bit to “0” (transmit and
receive disabled) simultaneously. (any one of data transmis-
sion and reception cannot be stopped.)
side by using an external clock, set all of the receive enable bit
(bit 5), the S
register (address 1A
put mode before data is written to the transmit/receive buffer
register.
2004.06.08
RDY
RDY
signal input is used, set the using pin to the in-
output enable bit (bit 2 of serial I/O control
16
)), and the transmit enable bit to “1”.
page 63 of 66
CLK
16
, and S
)) to “0” (serial I/O and transmit
RDY
RDY
function as I/O ports,
pin on the reception
16
)) to
(2) The transmit shift completion flag (bit 2 of serial I/O status reg-
(3) When data transmission is executed at the state that an exter-
(4) When the transmit interrupt is used, set as the following se-
register 1 (address 3E
<Reason>
When the transmit enable bit is set to “1”, the transmit buffer
empty flag (bit 0) and transmit shift completion flag (bit 2 of serial
I/O status register (address 19
Accordingly, even if the timing when any of the above flags is set
to “1” is selected for the transmit interrupt source, interrupt request
occurs and the transmit interrupt request bit is set.
(5) Write to the baud rate generator (BRG) while the transmit/re-
Fig. 7 Sequence of setting serial I/O control register again
3. Notes common to clock synchronous serial I/O and UART
(1) Set the serial I/O control register again after the transmission
Serial I/O transmit interrupt enable bit is set to “0” (disabled).
Serial I/O transmit enable bit is set to “1”.
Serial I/O transmit interrupt request bit (bit 1 of interrupt request
register 1 (address 3C
tions have been executed.
Serial I/O transmit interrupt enable bit (bit 1 of interrupt control
ister (address 19
0.5 to 1.5 shift clocks. When data transmission is controlled
with referring to the flag after writing the data to the transmit
buffer register, note the delay.
nal clock input is selected as the synchronous clock, set “1” to
the transmit enable bit while the S
to the transmit buffer register while the S
quence.
ceive operation is stopped.
and the reception circuits are reset by clearing both the trans-
mit enable bit and the receive enable bit to “0.”
Clear both the transmit enable bit (TE)
and the receive enable bit (RE) to “0”
Set the bits 0 to 3 and bit 6 of the
serial I/O control register
Set both the transmit enable bit (TE)
and the receive enable bit (RE), or
one of them to “1”
16
16
)) changes from “1” to “0” with a delay of
)) is set to “1” (enabled).
16
)) is set to “0” after 1 or more instruc-
16
)) are set to “1”.
CLK
is “H” state. Also, write
CLK
Can be set
with the LDM
instruction at
the same time
is “H” state.