M37544G2AGP#U0 Renesas Electronics America, M37544G2AGP#U0 Datasheet - Page 34

• Manufacturer Part Number: M37544G2AGP#U0
• Description: IC 740 MCU OTP 8K 32LQFP
• Manufacturer: Renesas Electronics America
• Series: 740/38000r

Specifications of M37544G2AGP#U0

• Core Processor: 740
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SIO, UART/USART
• Peripherals: WDT
• Number Of I /o: 25
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: QzROM
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 6x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Fig. 35 Block diagram of watchdog timer
Rev.1.04
REJ03B0012-0104Z
7544 Group
Watchdog Timer
The watchdog timer gives a means for returning to a reset status
when the program fails to run on its normal loop due to a runaway.
The watchdog timer consists of an 8-bit watchdog timer H and an
8-bit watchdog timer L, being a 16-bit counter.
Standard operation of watchdog timer
The watchdog timer stops when the watchdog timer control regis-
ter (address 0039
value to the watchdog timer control register (address 0039
causes the watchdog timer to start to count down. When the
watchdog timer H underflows, an internal reset occurs. Accord-
ingly, it is programmed that the watchdog timer control register
(address 0039
When the watchdog timer control register (address 0039
read, the values of the high-order 6-bit of the watchdog timer H,
STP instruction disable bit and watchdog timer H count source se-
lection bit are read.
Initial value of watchdog timer
By a reset or writing to the watchdog timer control register (ad-
dress 0039
watchdog timer L is set to “FF
Fig. 36 Structure of watchdog timer control register
X
IN
RESET
16
2004.06.08
), the watchdog timer H is set to “FF
16
) can be set before an underflow occurs.
b7
STP Instruction disable bit
16
) is not set after reset. Writing an optional
Write “FF
watchdog timer
control register
page 32 of 66
16
STP Instruction
”.
1/16
16
” to the
Watchdog timer L (8)
b0
Watchdog timer control register
(WDTCON: address 0039
16
” and the
Watchdog timer H (read only for high-order 6-bit)
STP instruction disable bit
0 : STP instruction enabled
1 : STP instruction disabled
Watchdog timer H count source selection bit
0 : Watchdog timer L underflow
1 : f(X
16
) is
16
IN
)
)/16
“0”
“1”
Watchdog timer H count
source selection bit
Operation of watchdog timer H count source selection bit
A watchdog timer H count source can be selected by bit 7 of the
watchdog timer control register (address 0039
“0”, the count source becomes a watchdog timer L underflow sig-
nal. The detection time is 131.072 ms at f(X
When this bit is “1”, the count source becomes f(X
case, the detection time is 512 s at f(X
This bit is cleared to “0” after reset.
Operation of STP instruction disable bit
When the watchdog timer is in operation, the STP instruction can
be disabled by bit 6 of the watchdog timer control register (ad-
dress 0039
When this bit is “0”, the STP instruction is enabled.
When this bit is “1”, the STP instruction is disabled, and an inter-
nal reset occurs if the STP instruction is executed.
Once this bit is set to “1”, it cannot be changed to “0” by program.
This bit is cleared to “0” after reset.
Watchdog timer H (8)
16
).
16
Reset
circuit
, initial value: 3F
Data bus
16
Internal
reset
IN
Write "FF
watchdog timer
control register
)
)=8 MHz.
IN
)=8 MHz.
16
). When this bit is
16
IN
" to the
)/16. In this