M37544G2AGP#U0 Renesas Electronics America, M37544G2AGP#U0 Datasheet - Page 26

• Manufacturer Part Number: M37544G2AGP#U0
• Description: IC 740 MCU OTP 8K 32LQFP
• Manufacturer: Renesas Electronics America
• Series: 740/38000r

Specifications of M37544G2AGP#U0

• Core Processor: 740
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SIO, UART/USART
• Peripherals: WDT
• Number Of I /o: 25
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: QzROM
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 6x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Rev.1.04
REJ03B0012-0104Z
7544 Group
Timer X is an 8-bit timer and counts the prescaler X output.
When Timer X underflows, the timer X interrupt request bit is set
to “1”.
Prescaler X is an 8-bit prescaler and counts the signal selected by
the timer X count source selection bit.
Prescaler X and Timer X have the prescaler X latch and the timer
X latch to retain the reload value, respectively. The value of
prescaler X latch is set to Prescaler X when Prescaler X
underflows. The value of timer X latch is set to Timer X when
Timer X underflows.
When writing to Prescaler X (PREX) and Timer X (TX) is ex-
ecuted, writing to “latch only” or “latch and prescaler (timer)” can
be selected by the setting value of the timer X write control bit.
When reading from Prescaler X (PREX) and Timer X (TX) is ex-
ecuted, each count value is read out.
Timer X can be selected in one of 4 operating modes by setting
the timer X operating mode bits of the timer X mode register.
(1) Timer mode
Prescaler X counts the count source selected by the timer X count
source selection bits. Each time the count clock is input, the con-
tents of Prescaler X is decremented by 1. When the contents of
Prescaler X reach “00
clock, and the prescaler X latch is reloaded into Prescaler X and
count continues. The division ratio of Prescaler X is 1/(n+1) pro-
vided that the value of Prescaler X is n.
The contents of Timer X is decremented by 1 each time the under-
flow signal of Prescaler X is input. When the contents of Timer X
reach “00
timer X latch is reloaded into Timer X and count continues. The di-
vision ratio of Timer X is 1/(m+1) provided that the value of Timer
X is m. Accordingly, the division ratio of Prescaler X and Timer X is
1/((n+1) (m+1)) provided that the value of Prescaler X is n and
the value of Timer X is m.
(2) Pulse output mode
In the pulse output mode, the waveform whose polarity is inverted
each time timer X underflows is output from the CNTR
The output level of CNTR
tive edge switch bit. When the CNTR
the output of CNTR
the output is started at “L” level.
Also, the inverted waveform of pulse output from CNTR
be output from TX
valid bit.
When using a timer in this mode, set the port P1
tion registers to output mode.
(3) Event counter mode
The timer A counts signals input from the P1
Except for this, the operation in event counter mode is the same
as in timer mode.
The active edge of CNTR
rising or falling by the CNTR
Timer X
16
”, an underflow occurs at the next count clock, and the
2004.06.08
OUT
0
pin is started at “H” level. When this bit is “1”,
16
pin by setting “1” to the P0
”, an underflow occurs at the next count
0
0
pin can be selected by the CNTR
page 24 of 66
pin input signal can be selected from
0
active edge switch bit .
0
active edge switch bit is “0”,
4
/CNTR
4
3
and P0
/TX
0
pin.
0
OUT
pin.
0
pin can
3
output
direc-
0
ac-
(4) Pulse width measurement mode
In the pulse width measurement mode, the pulse width of the sig-
nal input to P1
The operation of Timer X can be controlled by the level of the sig-
nal input from the CNTR
When the CNTR
by the timer X count source selection bit is counted while the input
signal level of CNTR
pin is “L”. Also, when the CNTR
signal selected by the timer X count source selection bit is
counted while the input signal level of CNTR
is stopped while the pin is “H”.
Timer X can stop counting by setting “1” to the timer X count stop
bit in any mode.
Also, when Timer X underflows, the timer X interrupt request bit is
set to “1”.
Note on Timer X is described below;
CNTR
CNTR
switch bit.
When this bit is “0”, the CNTR
the falling edge of CNTR
CNTR
CNTR
Note on Timer X
0
0
0
0
interrupt active edge selection
interrupt active edge depends on the CNTR
pin input signal.
interrupt request bit is set to “1” at the rising edge of
4
/CNTR
0
active edge switch bit is “0”, the signal selected
0
0
pin is “H”. The count is stopped while the
pin is measured.
0
0
pin.
pin input signal. When this bit is “1”, the
0
interrupt request bit is set to “1” at
0
active edge switch bit is “1”, the
0
pin is “L”. The count
0
active edge