PIC32MX360F512L-80I/PT Microchip Technology, PIC32MX360F512L-80I/PT Datasheet - Page 373

IC PIC MCU FLASH 512K 100-TQFP

PIC32MX360F512L-80I/PT

Manufacturer Part Number
PIC32MX360F512L-80I/PT
Description
IC PIC MCU FLASH 512K 100-TQFP
Manufacturer
Microchip Technology
Series
PIC® 32MXr

Specifications of PIC32MX360F512L-80I/PT

Program Memory Type
FLASH
Program Memory Size
512KB (512K x 8)
Package / Case
100-TFQFP
Core Processor
MIPS32® M4K™
Core Size
32-Bit
Speed
80MHz
Connectivity
I²C, IrDA, LIN, PMP, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
85
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC32MX3xx
Core
MIPS
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
I2C , SPI , UART
Maximum Clock Frequency
80 MHz
Number Of Programmable I/os
85
Number Of Timers
5 x 16 bit
Operating Supply Voltage
2.3 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, DM320001, DM320002, MA320001
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Controller Family/series
PIC32
No. Of I/o's
85
Ram Memory Size
32KB
Cpu Speed
80MHz
No. Of Timers
6
Embedded Interface Type
EUART, I2C, PSP, SPI
No. Of Pwm Channels
5
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
876-1000 - PIC32 BREAKOUT BOARDAC244003 - TEST BD MPLAB REAL ICE LOOPBACKAC244006 - KIT MPLAB REAL ICE TRACEDM320001 - KIT EVAL PIC32 STARTERAC164333 - MODULE SKT FOR PM3 100QFP
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

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16.1
There are three modes of operation that change the
state of the output pin; these modes can be referred to
as drive high, drive low and toggle. The configuration
for these modes is identical, the mode is selected by
the OCM bits. For this example, Tx will represent
Timer2.
Drive
(OCxCON<2:0>) are set to ‘001’, the selected output
compare channel initializes the OCx pin to the low state
and drives the output pin high when a compare event
occurs.
Drive
(OCxCON<2:0>) are set to ‘010’, the selected output
compare channel initializes the OCx pin to the high
state and drives the output pin low when a compare
event occurs.
Toggle: When the OCM control bits (OCxCON<2:0>)
are set to ‘011’, the selected output compare channel
OCx pin is not initialized. The OCx pin is driven to the
opposite state when a compare event occurs.
To generate a output change signal, the following steps
are required (these steps assume the timer source is
initially turned off, but this is not a requirement for the
module operation):
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. Upon the first match between TMRx and OCxR,
© 2008 Microchip Technology Inc.
Determine the timer clock cycle time. Take into
account the frequency of the external clock to
the timer source (if one is used) and the timer
prescaler settings.
Calculate time to the rising edge of the output
pulse relative to the timer start value (0000h).
Determine if the output compare module will be
used in 16 or 32-bit mode based on the previous
calculations.
Configure the timer to be used as the time base
for 16 or 32-bit mode by writing to the T32 bit
(TxCON<T32>).
Configure the output compare channel for 16 or
32-bit operation by writing to the OC32 bit
(OCxCON<5>).
Write the value computed in step 2 above into
the Compare register, OCxR.
Set Timer Period register, PRx, to the value equal
to or greater than the value in OCxRS, the
Secondary Compare register.
Set the OCM bits to the desired mode of operation
and the OCTSEL (OCxCON<3>) bit to the desired
timer source. The OCx pin state will now be driven
low.
Set the ON (TxCON<15>) bit to ‘1’ which enables
the compare time base to count.
the OCx pin will be driven high.
High:
Low:
Setup for Single Output Change
When
When
the
the
OCM
OCM
control
control
Advance Information
bits
bits
11. When the incrementing timer, TMRx, matches the
12. To initiate another single pulse output, change the
16.2
When the OCM control bits (OCxCON<2:0>) are set to
‘100’, the selected output compare channel initializes
the OCx pin to the low state and generates a single out-
put pulse.
To generate a single output pulse, the following steps
are required (these steps assume the timer source is
initially turned off, but this is not a requirement for the
module operation): For this example Tx will represent
Timer2.
1.
2.
3.
4.
5.
6.
7.
8.
Secondary Compare register, OCxRS, the
second and trailing edge (high-to-low) of the pulse
is driven onto the OCx pin. No additional pulses
are driven onto the OCx pin and it remains at low.
As a result of the second compare match event,
the OCxIF interrupt flag bit is set, which will
result in an interrupt if it is enabled, by setting
the OCxIE bit. For further information on
peripheral interrupts, refer to Section 8.0
“Interrupts”.
Timer and Compare register settings, if needed,
and then issue a write to set the OCM bits to the
desired mode of operation. Disabling and re-
enabling of the timer and clearing the Timer
register
advantageous for defining a pulse from a known
event time boundary.
Determine the timer clock cycle time. Take into
account the frequency of the external clock to
the timer source (if one is used) and the timer
prescaler settings.
Calculate time to the rising edge of the output
pulse relative to the timer start value (0000h).
Calculate the time to the falling edge of the pulse
based on the desired pulse width and the time to
the rising edge of the pulse.
Determine if the output compare module will be
used in 16 or 32-bit mode based on the previous
calculations.
Configure the timer to be used as the time base
for 16 or 32-bit mode by writing to the T32 bit
(TxCON<T32>).
Configure the output compare channel for 16 or
32-bit operation by writing to the OC32 bit
(OCxCON<5>).
Write the values computed in steps 2 and 3
above into the Compare register, OCxR, and the
Secondary
respectively.
Set Timer Period register, PRx, to the value equal
to or greater than the value in the OCxRS, the
Secondary Compare register.
PIC32MX FAMILY
Setup for Single Output Pulse
Generation
are
Compare
not
required,
register,
DS61143B-page 371
but
may
OCxRS,
be

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