PIC32MX360F512L-80I/PT Microchip Technology, PIC32MX360F512L-80I/PT Datasheet - Page 197

• Manufacturer Part Number: PIC32MX360F512L-80I/PT
• Description: IC PIC MCU FLASH 512K 100-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX360F512L-80I/PT

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-TFQFP
• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: I²C, IrDA, LIN, PMP, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 85
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC32MX3xx
• Core: MIPS
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C , SPI , UART
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 85
• Number Of Timers: 5 x 16 bit
• Operating Supply Voltage: 2.3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM320001, DM320002, MA320001
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: PIC32
• No. Of I/o's: 85
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• No. Of Timers: 6
• Embedded Interface Type: EUART, I2C, PSP, SPI
• No. Of Pwm Channels: 5
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1000 - PIC32 BREAKOUT BOARDAC244003 - TEST BD MPLAB REAL ICE LOOPBACKAC244006 - KIT MPLAB REAL ICE TRACEDM320001 - KIT EVAL PIC32 STARTERAC164333 - MODULE SKT FOR PM3 100QFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

9.3.4
When configured for predictive prefetch on cacheable
addresses, the module predicts the next line address
and returns it into the pseudo LRU line of the cache. If
enabled, the prefetch function starts predicting based
on the first CPU instruction fetch. When the first line is
placed in the cache, the module simply increments the
address to the next 16-byte aligned address and starts
a flash access. When running linear code (i.e. no
jumps), the flash returns the next set of instructions
into the prefetch buffer on or before all instructions can
be executed from the previous line.
If at any time during a predicted flash access, a new
CPU address does not match the predicted one, the
flash access will be changed to the correct address.
This behavior does not cause the CPU access to take
any longer than without prediction.
If an access that misses the cache hits the prefetch
buffer, the instructions are placed in the pseudo LRU
line along with its address tag. The pseudo LRU value
is marked as the most recently used line and other
lines are updated accordingly. If an access misses
both the cache and the prefetch buffer, the access
passes to the flash and those returning instructions
are placed in the pseudo LRU line.
When configured for predictive prefetch on non-cache-
able addresses, the controller only uses the prefetch
buffer. The LRU cache line is not updated for hits or
fills so the cache remains intact. For linear code,
enabling
addresses allows the CPU to fetch instructions in zero
Wait states.
It is not useful to use non-cacheable predictive
prefetching when accesses to the flash are set for zero
Wait states. The controller holds prefetched instruc-
tions on the output of the flash for up to 3 clock cycles
(while the CPU is fetching from the buffer). This con-
sumes more power without any benefit for zero Wait
state flash accesses.
Predictive data prefetching is not supported. However,
a data access in the middle of a predictive instruction
fetch causes the prefetch controller to stop the flash
access for the instruction fetch and to start the data
load from flash. The predictive prefetch does not
resume, but instead waits for another instruction fetch.
At which time, it either fills the buffer because of a
miss, or starts a prefetch because of a hit.
© 2008 Microchip Technology Inc.
predictive
PREDICTIVE PREFETCH
BEHAVIOR
prefetch
for
non-cacheable
Advance Information
9.3.5
It is not possible to execute out of cache while pro-
gramming the flash memory. The flash controller stalls
the cache during the programming sequence. There-
fore, user code that initiates a programming sequence
must not be located in a cacheable address region.
If CHECON.CHECOH = 1, then coherency is strictly
supported by invalidating, unlocking, and clearing
masks for all lines whenever the Flash Program
Memory is written or programmed.
If CHECON.CHECOH = 0, then only lines that are not
locked are forced invalid. Lines that are locked are
retained.
9.4
The prefetch module does not generate any interrupts.
Exceptions can occur if cache lines are marked as valid
manually by writing to individual CHETAG registers
then executing code that hits one of these lines contain-
ing invalid instructions. Also manually placing data into
an un-locked cache line may cause a coherency prob-
lem from an eviction due to a cache miss in the middle
of the loading algorithm.
9.4.1
The prefetch module does not use any external pins.
PIC32MX FAMILY
Prefetch Module Interrupts and
Exceptions
COHERENCY SUPPORT
I/O PIN CONFIGURATION
DS61143B-page 195