PIC18F6527-I/PT Microchip Technology, PIC18F6527-I/PT Datasheet - Page 3

• Manufacturer Part Number: PIC18F6527-I/PT
• Description: IC PIC MCU FLASH 24KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F6527-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 48KB (24K x 16)
• Package / Case: 64-TFQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 54
• Eeprom Size: 1K x 8
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3936 B
• Interface Type: SPI/I2C/EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183032
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12-ch x 10-bit
• Package: 64TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT64PT5 - SOCKET TRAN ICE 64MQFP/TQFPAC164319 - MODULE SKT MPLAB PM3 64TQFPDV007003 - PROGRAMMER UNIVERSAL PROMATE II
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

10. Module: EUSART
11. Module: EUSART
© 2006 Microchip Technology Inc.
In rare situations, one or more extra zero bytes
have been observed in a packet transmitted by the
module operating in Asynchronous mode. The
actual data is not lost or corrupted; only unwanted
(extra) zero bytes are observed in the packet.
This situation has only been observed when the
contents of the transmit buffer, TXREGx, are trans-
ferred to the TSRx during the transmission of a
Stop bit. For this to occur, three things must
happen in the same instruction cycle:
• TXREGx is written to;
• the baud rate counter overflows (at the end of
• a Stop bit is being transmitted (shifted out of
Work around
If possible, do not use the module’s double buffer
capability. Instead, load the TXREGx register
when the TRMT bit (TXSTAx<1>) is set, indicating
the TSRx is empty.
If double-buffering is used and back-to-back
transmission is performed, then load TXREGx
immediately after TXxIF is set or wait 1-bit time after
TXxIF is set. Both solutions prevent writing TXREGx
while a Stop bit is transmitted. Note that TXxIF is set
at the beginning of the Stop bit transmission.
When performing back-to-back transmission in 9-bit
mode (TX9D bit in the TXSTAx register is set), the
second byte may be corrupted if it is written into
TXREGx immediately after the TMRT bit is set.
Work around
Execute a software delay, at least one-half the
transmission’s bit time, after TMRT is set and prior
to writing subsequent bytes into TXREGx.
Date Codes that pertain to this issue:
All engineering and production devices.
If transmission is intermittent, then do the following:
Date Codes that pertain to this issue:
All engineering and production devices.
the bit period); and
TSRx).
• Wait for the TRMT bit to be set before
• Alternatively, use a free timer resource to time
loading TXREGx
the baud period. Set up the timer to overflow
at the end of the Stop bit, then start the timer
when you load the TXREGx. Do not load the
TXREGx when timer is about to overflow.
PIC18F6527/6622/8527/8622
12. Module: EUSART
13. Module: MSSP (SPI Mode)
Note:
With the auto-wake-up option enabled by setting
the WUE (BAUDCONx<1>) bit, the RCxIF bit will
become set on a high-to-low transition on the RXx
pin. However, the WUE bit may not clear within
1 T
WUE bit is set, reading the receive buffer,
RCREGx, will not clear the RCxIF interrupt flag.
Therefore, the first opportunity to automatically
clear RCxIF by reading RCREGx may take longer
than expected.
Work around
There are two work arounds available:
1. Clear the WUE bit in software, after the wake-
2. Poll the WUE bit and read RCREGx after the
Date Codes that pertain to this issue:
All engineering and production devices.
In SPI mode, the SDOx output may change after
the inactive clock edge of the bit ‘0’ output. This
may affect some SPI components that read data
over 300 ns after the inactive edge of SCKx.
Work around
None
Date Codes that pertain to this issue:
All engineering and production devices.
CY
up event has occurred, prior to reading the
receive buffer, RCREGx.
WUE bit is automatically cleared.
of a low-to-high transition on RXx. While the
RCxIF can only be cleared by reading
RCREGx.
DS80253B-page 3