PIC18F6527-I/PT Microchip Technology, PIC18F6527-I/PT Datasheet - Page 2

• Manufacturer Part Number: PIC18F6527-I/PT
• Description: IC PIC MCU FLASH 24KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F6527-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 48KB (24K x 16)
• Package / Case: 64-TFQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 54
• Eeprom Size: 1K x 8
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3936 B
• Interface Type: SPI/I2C/EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183032
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12-ch x 10-bit
• Package: 64TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT64PT5 - SOCKET TRAN ICE 64MQFP/TQFPAC164319 - MODULE SKT MPLAB PM3 64TQFPDV007003 - PROGRAMMER UNIVERSAL PROMATE II
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F6527/6622/8527/8622
4. Module: EUSART
5. Module: ECCP
6. Module: External Memory Bus
DS80253B-page 2
In 9-Bit Asynchronous Full-Duplex Receive mode,
received data may be corrupted if the TX9D bit
(TXSTAx<0>) is not modified immediately after
RCIDL (BAUDCONx<6>) is set.
Work around
Only write to TX9D when a reception is not in
progress (RCIDL = 1). No interrupt is associated
with RCIDL, therefore, it must be polled in software
to determine when TX9D can be updated.
PIC18F6XXX
CONFIG3L, is not unimplemented and will switch
the ECCP2 output pin similar to the PIC18F8XXX
devices if the Processor mode does not select
Microcontroller mode.
Work around
In MPLAB
as its PIC18F8XXX equivalent and assign the
Processor mode bits (PM<1:0>) to ‘11’ for
Microcontroller mode.
For PIC18F8XXX devices, the Stack Pointer may
incorrectly increment during a table read operation
if the external memory bus wait states are enabled
(i.e.,
(CONFIG3L<7> = 0) and WAIT<1:0> bits
(MEMCON<5:4>) are not equal to ‘11’).
Work around
If using the external memory bus and performing
TBLRD operations with a non-zero wait state
(CONFIG3L<7>
(MEMCON<5:4>) are not equal to ‘11’), disable
interrupts by clearing the GIE/GIEH (INTCON<7>)
and PEIE/GIEL (INTCON<6>) bits prior to executing
any TBLRD operation.
Configuration
®
IDE, program the PIC18F6XXX device
device’s
=
bit,
0
Configuration
and
WAIT,
WAIT<1:0>
is
Word,
clear
7. Module: MSSP
8. Module: Timer1
9. Module: PORTE
In SPI mode, the Buffer Full flag (BF bit in the
SSPxSTAT register), the Write Collision Detect bit
(WCOL bit in SSPxCON1) and the Receive
Overflow Indicator bit (SSPOV in SSPxCON1) are
not reset upon disabling the SPI module (by
clearing the SSPEN bit in the SSPxCON1
register).
For example, if SSPxBUF is full (BF bit is set) and
the MSSP module is disabled and re-enabled, the
BF bit will remain set. In SPI Slave mode, a sub-
sequent write to SSPxBUF will result in a write
collision. Also, if a new byte is received, a receive
overflow will occur.
Work around
Ensure that if the buffer is full, SSPxBUF is read
(thus clearing the BF flag) and WCOL is clear
before disabling the MSSP module. If the module
is configured in SPI Slave mode, ensure that the
SSPOV bit is clear before disabling the module.
In 16-Bit Asynchronous Counter mode or 16-Bit
Asynchronous Oscillator mode, the TMR1H and
TMR3H buffers do not update when TMRxL is
read. This issue only affects reading the TMRxH
registers. The timers increment and set the inter-
rupt flags as expected. The Timer registers can
also be written as expected.
Work around
Use 8-bit mode by clearing the RD16 (T1CON<7>)
bit or use the synchronization option by clearing
T1SYNC (T1CON<2>).
The RE4 pin latch remains at tri-state when the
ECCPMX Configuration bit is clear and selects
PORTH.
Work around
This issue will be corrected in a future revision of
silicon.
© 2006 Microchip Technology Inc.