PIC18F6410-I/PT Microchip Technology, PIC18F6410-I/PT Datasheet - Page 2

• Manufacturer Part Number: PIC18F6410-I/PT
• Description: IC PIC MCU FLASH 8KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F6410-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 16KB (8K x 16)
• Package / Case: 64-TFQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 54
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: SPI/I2C/EUSART/AUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 4
• Operating Supply Voltage: 4.2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183032
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12-ch x 10-bit
• Package: 64TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT64PT5 - SOCKET TRAN ICE 64MQFP/TQFPAC164319 - MODULE SKT MPLAB PM3 64TQFPDV007003 - PROGRAMMER UNIVERSAL PROMATE II
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F6310/6410/8310/8410
2. Module: MSSP
3. Module: MSSP
DS80206F-page 2
When the MSSP is configured for SPI Master
mode, the SDO pin cannot be disabled by setting
the TRISC<5> bit. The SDO pin always outputs
the content of SSPBUF regardless of the state of
the TRIS bit.
In Slave mode with Slave Select enabled,
SSPM3:SSPM0 = 0010 (SSPCON1<3:0>), the
SDO pin can be disabled by placing a logic high
level on the SS pin (RF7).
Work around
None.
Date Codes that pertain to this issue:
All engineering and production devices.
After an I
register may be written for up to 10 T
additional writes are blocked. The data transfer may
be corrupted if SSPBUF is written during this time.
The WCOL bit is set any time an SSPBUF write
occurs during a transfer.
Work around
Avoid writing SSPBUF until the data transfer is
complete, indicated by the setting of the SSPIF bit
(PIR1<3>).
Verify the WCOL bit (SSPCON1<7>) is clear after
writing SSPBUF to ensure any potential transfer in
progress is not corrupted.
Date Codes that pertain to this issue:
All engineering and production devices.
2
C transfer is initiated, the SSPBUF
CY
before
4. Module: MSSP
5. Module: MSSP
In 10-bit Addressing mode, when a Repeated Start
is issued followed by the high address byte and a
write command (R/W = 0), an ACK is not issued.
Work around
There are two work arounds available:
1. Single-Master Environment:
2. Multi-Master Environment:
Date Codes that pertain to this issue:
All engineering and production devices.
I
bit should be set) only when the system is idle
(i.e., when ACKEN, RCEN, PEN, RSEN and SEN
all equal zero). It should not be possible to set the
RCEN bit when the system is not idle, however,
the RCEN bit can be set under this circumstance.
Work around
Wait for the system to become idle before setting the
RCEN bit. This requires a check for the following bits
to be clear:
ACKEN, RCEN, PEN, RSEN and SEN.
Date Codes that pertain to this issue:
All engineering and production devices.
2
C Receive mode should be enabled (i.e., RCEN
In a single-master environment, the user must
issue a Stop, then a Start, followed by a write
to the address high, then the address low
followed by the data.
In a multi-master environment, the user must
issue a Repeated Start, send a dummy write
command to a different address, issue another
Repeated Start and then send a write to the
original address. This procedure will help
maintain control of the bus.
© 2007 Microchip Technology Inc.